Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, expo...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2012-06-01
|
| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2079-9268/2/2/180 |
| _version_ | 1811307300933074944 |
|---|---|
| author | Lauri Koskinen Matthew J. Turnquist Erkka Laulainen Jani Mäkipää |
| author_facet | Lauri Koskinen Matthew J. Turnquist Erkka Laulainen Jani Mäkipää |
| author_sort | Lauri Koskinen |
| collection | DOAJ |
| description | This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm<sup>2</sup>, and operates down to 300 mV. |
| first_indexed | 2024-04-13T09:02:09Z |
| format | Article |
| id | doaj.art-5877aadf27d146b68c44d6d8ae475441 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-13T09:02:09Z |
| publishDate | 2012-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-5877aadf27d146b68c44d6d8ae4754412022-12-22T02:53:07ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682012-06-012218019610.3390/jlpea2020180Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOSLauri KoskinenMatthew J. TurnquistErkka LaulainenJani MäkipääThis paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm<sup>2</sup>, and operates down to 300 mV.http://www.mdpi.com/2079-9268/2/2/180subthresholdultra-low-powertiming-error detectionsubthreshold source-coupled logicSCLweak inversiondynamic supply voltagedynamic voltage scaling |
| spellingShingle | Lauri Koskinen Matthew J. Turnquist Erkka Laulainen Jani Mäkipää Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS Journal of Low Power Electronics and Applications subthreshold ultra-low-power timing-error detection subthreshold source-coupled logic SCL weak inversion dynamic supply voltage dynamic voltage scaling |
| title | Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS |
| title_full | Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS |
| title_fullStr | Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS |
| title_full_unstemmed | Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS |
| title_short | Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS |
| title_sort | timing error detection design considerations in subthreshold an 8 bit microprocessor in 65 nm cmos |
| topic | subthreshold ultra-low-power timing-error detection subthreshold source-coupled logic SCL weak inversion dynamic supply voltage dynamic voltage scaling |
| url | http://www.mdpi.com/2079-9268/2/2/180 |
| work_keys_str_mv | AT laurikoskinen timingerrordetectiondesignconsiderationsinsubthresholdan8bitmicroprocessorin65nmcmos AT matthewjturnquist timingerrordetectiondesignconsiderationsinsubthresholdan8bitmicroprocessorin65nmcmos AT erkkalaulainen timingerrordetectiondesignconsiderationsinsubthresholdan8bitmicroprocessorin65nmcmos AT janimakipaa timingerrordetectiondesignconsiderationsinsubthresholdan8bitmicroprocessorin65nmcmos |