Design and Analysis of an Approximate Adder with Hybrid Error Reduction
This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts...
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| Format: | Article |
| Language: | English |
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MDPI AG
2020-03-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/3/471 |
| _version_ | 1797999064521900032 |
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| author | Hyoju Seo Yoon Seok Yang Yongtae Kim |
| author_facet | Hyoju Seo Yoon Seok Yang Yongtae Kim |
| author_sort | Hyoju Seo |
| collection | DOAJ |
| description | This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders. |
| first_indexed | 2024-04-11T10:58:39Z |
| format | Article |
| id | doaj.art-5a7aa903f718411a8d26942125aadb74 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-04-11T10:58:39Z |
| publishDate | 2020-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-5a7aa903f718411a8d26942125aadb742022-12-22T04:28:41ZengMDPI AGElectronics2079-92922020-03-019347110.3390/electronics9030471electronics9030471Design and Analysis of an Approximate Adder with Hybrid Error ReductionHyoju Seo0Yoon Seok Yang1Yongtae Kim2School of Computer Science and Engineering, Kyungpook National University, Daegu 41566, KoreaIntel Labs, Intel Corporation, Santa Clara, CA 95054, USASchool of Computer Science and Engineering, Kyungpook National University, Daegu 41566, KoreaThis paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.https://www.mdpi.com/2079-9292/9/3/471approximate adderapproximate computinghybrid error reductionlow powerenergy efficiency |
| spellingShingle | Hyoju Seo Yoon Seok Yang Yongtae Kim Design and Analysis of an Approximate Adder with Hybrid Error Reduction Electronics approximate adder approximate computing hybrid error reduction low power energy efficiency |
| title | Design and Analysis of an Approximate Adder with Hybrid Error Reduction |
| title_full | Design and Analysis of an Approximate Adder with Hybrid Error Reduction |
| title_fullStr | Design and Analysis of an Approximate Adder with Hybrid Error Reduction |
| title_full_unstemmed | Design and Analysis of an Approximate Adder with Hybrid Error Reduction |
| title_short | Design and Analysis of an Approximate Adder with Hybrid Error Reduction |
| title_sort | design and analysis of an approximate adder with hybrid error reduction |
| topic | approximate adder approximate computing hybrid error reduction low power energy efficiency |
| url | https://www.mdpi.com/2079-9292/9/3/471 |
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