Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Design and Analysis of an Approximate Adder with Hybrid Error Reduction

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts...

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Bibliographic Details
Main Authors: Hyoju Seo, Yoon Seok Yang, Yongtae Kim
Format: Article
Language:English
Published: MDPI AG 2020-03-01
Series:Electronics
Subjects:
approximate adder
approximate computing
hybrid error reduction
low power
energy efficiency
Online Access:https://www.mdpi.com/2079-9292/9/3/471

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