Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support
Modern Field Programmable Gate Arrays (FPGA) are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC) primarily because o...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
International Science and Engineering Society, o.s.
2015-05-01
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| Series: | International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems |
| Online Access: | http://ijates.org/index.php/ijates/article/view/115 |
| _version_ | 1818522836455653376 |
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| author | Burhan Khurshid Roohie Naaz Mir |
| author_facet | Burhan Khurshid Roohie Naaz Mir |
| author_sort | Burhan Khurshid |
| collection | DOAJ |
| description | Modern Field Programmable Gate Arrays (FPGA) are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC) primarily because of the low Non-recurring Engineering (NRE) costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP) cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources. |
| first_indexed | 2024-12-11T05:38:05Z |
| format | Article |
| id | doaj.art-5bde73501c354967a41c9ff37831b32d |
| institution | Directory Open Access Journal |
| issn | 1805-5443 |
| language | English |
| last_indexed | 2024-12-11T05:38:05Z |
| publishDate | 2015-05-01 |
| publisher | International Science and Engineering Society, o.s. |
| record_format | Article |
| series | International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems |
| spelling | doaj.art-5bde73501c354967a41c9ff37831b32d2022-12-22T01:19:13ZengInternational Science and Engineering Society, o.s.International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems1805-54432015-05-0142334010.11601/ijates.v4i2.11574Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro supportBurhan Khurshid0Roohie Naaz Mir1Department of Computer Science and Engineering, NIT, Srinagar, J & K, IndiaDepartment of Computer Science and Engineering, NIT, Srinagar, J & K, IndiaModern Field Programmable Gate Arrays (FPGA) are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC) primarily because of the low Non-recurring Engineering (NRE) costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP) cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.http://ijates.org/index.php/ijates/article/view/115 |
| spellingShingle | Burhan Khurshid Roohie Naaz Mir Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems |
| title | Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support |
| title_full | Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support |
| title_fullStr | Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support |
| title_full_unstemmed | Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support |
| title_short | Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support |
| title_sort | achieving performance speed up in fpga based bit parallel multipliers using embedded primitive and macro support |
| url | http://ijates.org/index.php/ijates/article/view/115 |
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