Design of Low-Power ECG Sampling and Compression Circuit
Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) an...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-03-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/13/5/3350 |
| _version_ | 1797615649661386752 |
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| author | Zuoqin Zhao Yufei Nai Zhiguo Yu Xin Xu Xiaoyang Cao Xiaofeng Gu |
| author_facet | Zuoqin Zhao Yufei Nai Zhiguo Yu Xin Xu Xiaoyang Cao Xiaofeng Gu |
| author_sort | Zuoqin Zhao |
| collection | DOAJ |
| description | Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm<sup>2</sup> and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm<sup>2</sup>, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality. |
| first_indexed | 2024-03-11T07:29:42Z |
| format | Article |
| id | doaj.art-5c11ceac86fb4259aea411307b0dd81d |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-11T07:29:42Z |
| publishDate | 2023-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-5c11ceac86fb4259aea411307b0dd81d2023-11-17T07:22:36ZengMDPI AGApplied Sciences2076-34172023-03-01135335010.3390/app13053350Design of Low-Power ECG Sampling and Compression CircuitZuoqin Zhao0Yufei Nai1Zhiguo Yu2Xin Xu3Xiaoyang Cao4Xiaofeng Gu5Engineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaEngineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaEngineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaEngineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaEngineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaEngineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, ChinaCompressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm<sup>2</sup> and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm<sup>2</sup>, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality.https://www.mdpi.com/2076-3417/13/5/3350compressed sensingelectrocardiogramwireless sensor networksanalog-to-digital converterapproximation calculation |
| spellingShingle | Zuoqin Zhao Yufei Nai Zhiguo Yu Xin Xu Xiaoyang Cao Xiaofeng Gu Design of Low-Power ECG Sampling and Compression Circuit Applied Sciences compressed sensing electrocardiogram wireless sensor networks analog-to-digital converter approximation calculation |
| title | Design of Low-Power ECG Sampling and Compression Circuit |
| title_full | Design of Low-Power ECG Sampling and Compression Circuit |
| title_fullStr | Design of Low-Power ECG Sampling and Compression Circuit |
| title_full_unstemmed | Design of Low-Power ECG Sampling and Compression Circuit |
| title_short | Design of Low-Power ECG Sampling and Compression Circuit |
| title_sort | design of low power ecg sampling and compression circuit |
| topic | compressed sensing electrocardiogram wireless sensor networks analog-to-digital converter approximation calculation |
| url | https://www.mdpi.com/2076-3417/13/5/3350 |
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