An efficient common source sense amplifier for single ended SRAM
Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) f...
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| Format: | Article |
| Language: | English |
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Elsevier
2023-10-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064623000427 |
| _version_ | 1797656117449326592 |
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| author | Jebamalar Leavline Sugantha A. |
| author_facet | Jebamalar Leavline Sugantha A. |
| author_sort | Jebamalar Leavline |
| collection | DOAJ |
| description | Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture. |
| first_indexed | 2024-03-11T17:24:43Z |
| format | Article |
| id | doaj.art-5d13ae6247de4024b60973a070c1ff2c |
| institution | Directory Open Access Journal |
| issn | 2773-0646 |
| language | English |
| last_indexed | 2024-03-11T17:24:43Z |
| publishDate | 2023-10-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj.art-5d13ae6247de4024b60973a070c1ff2c2023-10-19T04:23:05ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462023-10-015100065An efficient common source sense amplifier for single ended SRAMJebamalar Leavline0Sugantha A.1Corresponding author.; Department of ECE, University College of Engineering, BIT Campus, Anna University, Tiruchirappalli, IndiaDepartment of ECE, University College of Engineering, BIT Campus, Anna University, Tiruchirappalli, IndiaSense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture.http://www.sciencedirect.com/science/article/pii/S2773064623000427Sensing timeSensing powerStatic random-access memory (SRAM)Single ended sensingCommon source amplifier |
| spellingShingle | Jebamalar Leavline Sugantha A. An efficient common source sense amplifier for single ended SRAM Memories - Materials, Devices, Circuits and Systems Sensing time Sensing power Static random-access memory (SRAM) Single ended sensing Common source amplifier |
| title | An efficient common source sense amplifier for single ended SRAM |
| title_full | An efficient common source sense amplifier for single ended SRAM |
| title_fullStr | An efficient common source sense amplifier for single ended SRAM |
| title_full_unstemmed | An efficient common source sense amplifier for single ended SRAM |
| title_short | An efficient common source sense amplifier for single ended SRAM |
| title_sort | efficient common source sense amplifier for single ended sram |
| topic | Sensing time Sensing power Static random-access memory (SRAM) Single ended sensing Common source amplifier |
| url | http://www.sciencedirect.com/science/article/pii/S2773064623000427 |
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