| Summary: | After lead-free technology, pre-existing voids in Power-MOSFET device solder connections have been a hot topic. Previous studies have examined the mechanical performance of solders with manufacturing-induced voids typically by generating excessive voids intentionally using simulation analysis without/insufficient experimental results. Electronic assembly standards such as IEC 61191-2, J-STD-001G, and IPC-A-610G do not cover voiding due to conflicting opinions and insufficient experimental evidence. In this context, comprehensive experimental results are needed to verify simulation results and assist in setting the standard. Silicon-based Power MOSFET packages with different locations, sizes, and patterns of pre-existing voids with nearly the same percentage of voids (30–33%) have been chosen to address this critical issue. The Power MOSFET test samples underwent power cycling-based accelerated degradation testing at various stress levels and monitored the location and rate of solder degradation at specific time intervals. It is found that small dispersive voids in solder life are useful, but clusters can accelerate damage propagation. Contrary, large dispersive voids at the edges initiate solder damage, reducing solder life. Our experimental investigation findings indicate that pre-existing voids' positions, sizes, and patterns should be considered when establishing solder void inspection standards. This would improve power devices' reliability for end-user power supply and control.
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