Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numeri...
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| Format: | Article |
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Beilstein-Institut
2012-12-01
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| Series: | Beilstein Journal of Nanotechnology |
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| Online Access: | https://doi.org/10.3762/bjnano.3.91 |
| _version_ | 1828920456879538176 |
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| author | Farhad Larki Arash Dehzangi Alam Abedini Ahmad Makarimi Abdullah Elias Saion Sabar D. Hutagalung Mohd N. Hamidon Jumiah Hassan |
| author_facet | Farhad Larki Arash Dehzangi Alam Abedini Ahmad Makarimi Abdullah Elias Saion Sabar D. Hutagalung Mohd N. Hamidon Jumiah Hassan |
| author_sort | Farhad Larki |
| collection | DOAJ |
| description | A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current. |
| first_indexed | 2024-12-13T21:45:09Z |
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| id | doaj.art-5d6bfb1d4af2486c8854be4b80c2d8f6 |
| institution | Directory Open Access Journal |
| issn | 2190-4286 |
| language | English |
| last_indexed | 2024-12-13T21:45:09Z |
| publishDate | 2012-12-01 |
| publisher | Beilstein-Institut |
| record_format | Article |
| series | Beilstein Journal of Nanotechnology |
| spelling | doaj.art-5d6bfb1d4af2486c8854be4b80c2d8f62022-12-21T23:30:25ZengBeilstein-InstitutBeilstein Journal of Nanotechnology2190-42862012-12-013181782310.3762/bjnano.3.912190-4286-3-91Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithographyFarhad Larki0Arash Dehzangi1Alam Abedini2Ahmad Makarimi Abdullah3Elias Saion4Sabar D. Hutagalung5Mohd N. Hamidon6Jumiah Hassan7Department of Physics, Universiti Putra Malaysia, 43400 Serdang, Selangor, MalaysiaInstitute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, MalaysiaDepartment of Physics, Universiti Putra Malaysia, 43400 Serdang, Selangor, MalaysiaSchool of Materials and Mineral Resources Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia,Department of Physics, Universiti Putra Malaysia, 43400 Serdang, Selangor, MalaysiaSchool of Materials and Mineral Resources Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia,Functional Devices Laboratory, Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor, MalaysiaDepartment of Physics, Universiti Putra Malaysia, 43400 Serdang, Selangor, MalaysiaA double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.https://doi.org/10.3762/bjnano.3.91AFM nanolithographyjunctionless transistorspinch-offscanning probe microscopesimulation |
| spellingShingle | Farhad Larki Arash Dehzangi Alam Abedini Ahmad Makarimi Abdullah Elias Saion Sabar D. Hutagalung Mohd N. Hamidon Jumiah Hassan Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography Beilstein Journal of Nanotechnology AFM nanolithography junctionless transistors pinch-off scanning probe microscope simulation |
| title | Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography |
| title_full | Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography |
| title_fullStr | Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography |
| title_full_unstemmed | Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography |
| title_short | Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography |
| title_sort | pinch off mechanism in double lateral gate junctionless transistors fabricated by scanning probe microscope based lithography |
| topic | AFM nanolithography junctionless transistors pinch-off scanning probe microscope simulation |
| url | https://doi.org/10.3762/bjnano.3.91 |
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