MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization

Inspired by the behavior of natural systems, Cellular Automata (CA) tackle the demanding long-distance information transfer of conventional computers by the massive parallel computation performed by a set of locally-coupled dynamical nodes. Although CA are envisioned as powerful deterministic comput...

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Main Authors: Vasileios Ntinas, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Nikolaos Vasileiadis, Panagiotis Dimitrakis, Antonio Rubio, Georgios Ch. Sirakoulis
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10121034/
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author Vasileios Ntinas
Iosif-Angelos Fyrigos
Rafailia-Eleni Karamani
Nikolaos Vasileiadis
Panagiotis Dimitrakis
Antonio Rubio
Georgios Ch. Sirakoulis
author_facet Vasileios Ntinas
Iosif-Angelos Fyrigos
Rafailia-Eleni Karamani
Nikolaos Vasileiadis
Panagiotis Dimitrakis
Antonio Rubio
Georgios Ch. Sirakoulis
author_sort Vasileios Ntinas
collection DOAJ
description Inspired by the behavior of natural systems, Cellular Automata (CA) tackle the demanding long-distance information transfer of conventional computers by the massive parallel computation performed by a set of locally-coupled dynamical nodes. Although CA are envisioned as powerful deterministic computers, their intrinsic capabilities are expanded after the memristor’s probabilistic switching is introduced into CA cells, resulting in new hybrid deterministic and probabilistic memristor-based CA (MemCA). In the proposed MemCA hardware realization, memristor devices are incorporated in both the cell and rule modules, composing the very first all-memristor CA hardware, designed with mixed CMOS/Memristor circuits. The proposed implementation accomplishes high operating speed and reduced area requirements, exploiting also memristor as an entropy source in every CA cell. MemCA’s functioning is showcased in deterministic and probabilistic operation, which can be externally modified by the selection of programming voltage amplitude, without changing the design. Also, the proposed MemCA system includes a reconfigurable rule module implementation that allows for spatial and temporal rule inhomogeneity.
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spelling doaj.art-5eb7dfe02ba64b39834d31b1fcdb97652023-06-12T23:01:46ZengIEEEIEEE Access2169-35362023-01-0111457824579710.1109/ACCESS.2023.327389910121034MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware RealizationVasileios Ntinas0https://orcid.org/0000-0002-2367-5567Iosif-Angelos Fyrigos1https://orcid.org/0000-0001-8032-1725Rafailia-Eleni Karamani2https://orcid.org/0000-0002-1856-1813Nikolaos Vasileiadis3https://orcid.org/0000-0002-6245-7220Panagiotis Dimitrakis4https://orcid.org/0000-0002-4941-0487Antonio Rubio5https://orcid.org/0000-0003-1625-1472Georgios Ch. Sirakoulis6https://orcid.org/0000-0001-8240-484XDepartment of Electronics Engineering, Universitat Politécnica de Catalunya (UPC), Barcelona, SpainDepartment of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, GreeceDepartment of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, GreeceDepartment of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, GreeceInstitute of Nanoscience and Nanotechnology, National Center for Scientific Research ``Demokritos'' (NCSR), Athens, GreeceDepartment of Electronics Engineering, Universitat Politécnica de Catalunya (UPC), Barcelona, SpainDepartment of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, GreeceInspired by the behavior of natural systems, Cellular Automata (CA) tackle the demanding long-distance information transfer of conventional computers by the massive parallel computation performed by a set of locally-coupled dynamical nodes. Although CA are envisioned as powerful deterministic computers, their intrinsic capabilities are expanded after the memristor’s probabilistic switching is introduced into CA cells, resulting in new hybrid deterministic and probabilistic memristor-based CA (MemCA). In the proposed MemCA hardware realization, memristor devices are incorporated in both the cell and rule modules, composing the very first all-memristor CA hardware, designed with mixed CMOS/Memristor circuits. The proposed implementation accomplishes high operating speed and reduced area requirements, exploiting also memristor as an entropy source in every CA cell. MemCA’s functioning is showcased in deterministic and probabilistic operation, which can be externally modified by the selection of programming voltage amplitude, without changing the design. Also, the proposed MemCA system includes a reconfigurable rule module implementation that allows for spatial and temporal rule inhomogeneity.https://ieeexplore.ieee.org/document/10121034/Memristor technologycellular automataemergent computing hardwarehybrid CMOS/memristor design
spellingShingle Vasileios Ntinas
Iosif-Angelos Fyrigos
Rafailia-Eleni Karamani
Nikolaos Vasileiadis
Panagiotis Dimitrakis
Antonio Rubio
Georgios Ch. Sirakoulis
MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
IEEE Access
Memristor technology
cellular automata
emergent computing hardware
hybrid CMOS/memristor design
title MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
title_full MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
title_fullStr MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
title_full_unstemmed MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
title_short MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization
title_sort memca all memristor design for deterministic and probabilistic cellular automata hardware realization
topic Memristor technology
cellular automata
emergent computing hardware
hybrid CMOS/memristor design
url https://ieeexplore.ieee.org/document/10121034/
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