Low Cost Test Pattern Generation in Scan-Based BIST Schemes

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input c...

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Main Authors: Guohe Zhang, Ye Yuan, Feng Liang, Sufen Wei, Cheng-Fu Yang
Format: Article
Language:English
Published: MDPI AG 2019-03-01
Series:Electronics
Subjects:
Online Access:http://www.mdpi.com/2079-9292/8/3/314
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author Guohe Zhang
Ye Yuan
Feng Liang
Sufen Wei
Cheng-Fu Yang
author_facet Guohe Zhang
Ye Yuan
Feng Liang
Sufen Wei
Cheng-Fu Yang
author_sort Guohe Zhang
collection DOAJ
description This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.
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spelling doaj.art-5f270b599535481b9ce00ad11a092f6a2022-12-22T04:23:24ZengMDPI AGElectronics2079-92922019-03-018331410.3390/electronics8030314electronics8030314Low Cost Test Pattern Generation in Scan-Based BIST SchemesGuohe Zhang0Ye Yuan1Feng Liang2Sufen Wei3Cheng-Fu Yang4School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, ChinaSchool of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, ChinaSchool of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, ChinaSchool of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, ChinaDepartment of Chemical and Materials Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nan-Tzu District, Kaohsiung 811, TaiwanThis paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.http://www.mdpi.com/2079-9292/8/3/314test pattern generationbuilt-in self-testbroadcast circuitlow cost
spellingShingle Guohe Zhang
Ye Yuan
Feng Liang
Sufen Wei
Cheng-Fu Yang
Low Cost Test Pattern Generation in Scan-Based BIST Schemes
Electronics
test pattern generation
built-in self-test
broadcast circuit
low cost
title Low Cost Test Pattern Generation in Scan-Based BIST Schemes
title_full Low Cost Test Pattern Generation in Scan-Based BIST Schemes
title_fullStr Low Cost Test Pattern Generation in Scan-Based BIST Schemes
title_full_unstemmed Low Cost Test Pattern Generation in Scan-Based BIST Schemes
title_short Low Cost Test Pattern Generation in Scan-Based BIST Schemes
title_sort low cost test pattern generation in scan based bist schemes
topic test pattern generation
built-in self-test
broadcast circuit
low cost
url http://www.mdpi.com/2079-9292/8/3/314
work_keys_str_mv AT guohezhang lowcosttestpatterngenerationinscanbasedbistschemes
AT yeyuan lowcosttestpatterngenerationinscanbasedbistschemes
AT fengliang lowcosttestpatterngenerationinscanbasedbistschemes
AT sufenwei lowcosttestpatterngenerationinscanbasedbistschemes
AT chengfuyang lowcosttestpatterngenerationinscanbasedbistschemes