An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache
An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9229177/ |
| _version_ | 1831808564652408832 |
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| author | Tae Hyun Kim Hanwool Jeong Juhyun Park Hoonki Kim Taejoong Song Seong-Ook Jung |
| author_facet | Tae Hyun Kim Hanwool Jeong Juhyun Park Hoonki Kim Taejoong Song Seong-Ook Jung |
| author_sort | Tae Hyun Kim |
| collection | DOAJ |
| description | An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches. |
| first_indexed | 2024-12-22T20:26:47Z |
| format | Article |
| id | doaj.art-5f2d61c91b2b4227b032f18d9b07faa7 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-22T20:26:47Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-5f2d61c91b2b4227b032f18d9b07faa72022-12-21T18:13:43ZengIEEEIEEE Access2169-35362020-01-01818712618713910.1109/ACCESS.2020.30300999229177An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power CacheTae Hyun Kim0Hanwool Jeong1Juhyun Park2https://orcid.org/0000-0003-4631-442XHoonki Kim3https://orcid.org/0000-0003-0720-6821Taejoong Song4https://orcid.org/0000-0003-2752-3138Seong-Ook Jung5https://orcid.org/0000-0003-0757-2581School of Electrical and Electronic Engineering, Yonsei University, Seoul, South KoreaDepartment of Electronic Engineering, Kwangwoon University, Seoul, South KoreaVolume Product Design Group, DRAM Design Division, SK Hynix Inc., Icheon, South KoreaFoundry Division, Samsung Electronics, Gyeonggi, South KoreaFoundry Division, Samsung Electronics, Gyeonggi, South KoreaSchool of Electrical and Electronic Engineering, Yonsei University, Seoul, South KoreaAn embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.https://ieeexplore.ieee.org/document/9229177/Dual-rail SRAMstatic random access memorycacheenergy-savingsGem5~simulatorlow-power operation |
| spellingShingle | Tae Hyun Kim Hanwool Jeong Juhyun Park Hoonki Kim Taejoong Song Seong-Ook Jung An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache IEEE Access Dual-rail SRAM static random access memory cache energy-savings Gem5~simulator low-power operation |
| title | An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
| title_full | An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
| title_fullStr | An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
| title_full_unstemmed | An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
| title_short | An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
| title_sort | embedded level shifting dual rail sram for high speed and low power cache |
| topic | Dual-rail SRAM static random access memory cache energy-savings Gem5~simulator low-power operation |
| url | https://ieeexplore.ieee.org/document/9229177/ |
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