Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System
ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to...
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| Format: | Article |
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MDPI AG
2020-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/9/1482 |
| _version_ | 1797554129973805056 |
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| author | Rafał Kiełbik Kamil Rudnicki Zbigniew Mudza Jarosław Jung |
| author_facet | Rafał Kiełbik Kamil Rudnicki Zbigniew Mudza Jarosław Jung |
| author_sort | Rafał Kiełbik |
| collection | DOAJ |
| description | ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier. |
| first_indexed | 2024-03-10T16:26:24Z |
| format | Article |
| id | doaj.art-610e37346fa84bc884e4cf145351dd8a |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T16:26:24Z |
| publishDate | 2020-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-610e37346fa84bc884e4cf145351dd8a2023-11-20T13:10:50ZengMDPI AGElectronics2079-92922020-09-0199148210.3390/electronics9091482Methodology of Firmware Development for ARUZ—An FPGA-Based HPC SystemRafał Kiełbik0Kamil Rudnicki1Zbigniew Mudza2Jarosław Jung3Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Łódź, PolandDepartment of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Łódź, PolandDepartment of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Łódź, PolandDepartment of Molecular Physics, Lodz University of Technology, ul. Żeromskiego 116, 90-924 Łódź, PolandARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier.https://www.mdpi.com/2079-9292/9/9/1482computer aided engineeringdesign automationhigh level synthesishigh performance computingprogrammable logic arraysreconfigurable architectures |
| spellingShingle | Rafał Kiełbik Kamil Rudnicki Zbigniew Mudza Jarosław Jung Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System Electronics computer aided engineering design automation high level synthesis high performance computing programmable logic arrays reconfigurable architectures |
| title | Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System |
| title_full | Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System |
| title_fullStr | Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System |
| title_full_unstemmed | Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System |
| title_short | Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System |
| title_sort | methodology of firmware development for aruz an fpga based hpc system |
| topic | computer aided engineering design automation high level synthesis high performance computing programmable logic arrays reconfigurable architectures |
| url | https://www.mdpi.com/2079-9292/9/9/1482 |
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