On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller
The paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic op...
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| Format: | Article |
| Language: | English |
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VSB-Technical University of Ostrava
2014-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/1134 |
| _version_ | 1797827033132171264 |
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| author | Adam Milik |
| author_facet | Adam Milik |
| author_sort | Adam Milik |
| collection | DOAJ |
| description | The paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic operations in a single clock cycle independently from the number of processed rungs. The paper considers the compilation of the ladder diagram into an intermediate form suitable for logic synthesis process according to developed processing method. The enhanced data flow graph (EDFG) has been developed for the intermediate representation of an LD program. The original construction of the EDFG with attributed edges has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that allow to preserve serial analysis order and to obtain massively parallel processing unit are presented. The overview of a hardware mapping concludes the presented considerations. |
| first_indexed | 2024-04-09T12:41:50Z |
| format | Article |
| id | doaj.art-61de6a0b3cd346ee8dca6f0f6de56b7b |
| institution | Directory Open Access Journal |
| issn | 1336-1376 1804-3119 |
| language | English |
| last_indexed | 2024-04-09T12:41:50Z |
| publishDate | 2014-01-01 |
| publisher | VSB-Technical University of Ostrava |
| record_format | Article |
| series | Advances in Electrical and Electronic Engineering |
| spelling | doaj.art-61de6a0b3cd346ee8dca6f0f6de56b7b2023-05-14T20:50:09ZengVSB-Technical University of OstravaAdvances in Electrical and Electronic Engineering1336-13761804-31192014-01-0112544345110.15598/aeee.v12i5.1134690On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic ControllerAdam Milik0Institute of Electronics Silesian University of TechnologyThe paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic operations in a single clock cycle independently from the number of processed rungs. The paper considers the compilation of the ladder diagram into an intermediate form suitable for logic synthesis process according to developed processing method. The enhanced data flow graph (EDFG) has been developed for the intermediate representation of an LD program. The original construction of the EDFG with attributed edges has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that allow to preserve serial analysis order and to obtain massively parallel processing unit are presented. The overview of a hardware mapping concludes the presented considerations.http://advances.utc.sk/index.php/AEEE/article/view/1134dfgfpgahigh-level synthesisiec61131-3ldlogic synthesisplcreconfigurable hardware. |
| spellingShingle | Adam Milik On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller Advances in Electrical and Electronic Engineering dfg fpga high-level synthesis iec61131-3 ld logic synthesis plc reconfigurable hardware. |
| title | On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller |
| title_full | On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller |
| title_fullStr | On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller |
| title_full_unstemmed | On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller |
| title_short | On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller |
| title_sort | on ladder diagrams compilation and synthesis to fpga implemented reconfigurable logic controller |
| topic | dfg fpga high-level synthesis iec61131-3 ld logic synthesis plc reconfigurable hardware. |
| url | http://advances.utc.sk/index.php/AEEE/article/view/1134 |
| work_keys_str_mv | AT adammilik onladderdiagramscompilationandsynthesistofpgaimplementedreconfigurablelogiccontroller |