On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller
The paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic op...
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| Format: | Article |
| Language: | English |
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VSB-Technical University of Ostrava
2014-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
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| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/1134 |