Quasi delay insensitive implementation of approximate multiplication
Asynchronous quasi delay insensitive (QDI) implementation of approximate multiplication is described in this article. We consider the array multiplier architecture for a QDI implementation. We obtain approximate QDI array multipliers by introducing vertical cuts in an accurate QDI array multiplier a...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Elsevier
2022-05-01
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| Series: | Ain Shams Engineering Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2090447921003944 |
| _version_ | 1828756933739282432 |
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| author | Padmanabhan Balasubramanian Nikos E. Mastorakis |
| author_facet | Padmanabhan Balasubramanian Nikos E. Mastorakis |
| author_sort | Padmanabhan Balasubramanian |
| collection | DOAJ |
| description | Asynchronous quasi delay insensitive (QDI) implementation of approximate multiplication is described in this article. We consider the array multiplier architecture for a QDI implementation. We obtain approximate QDI array multipliers by introducing vertical cuts in an accurate QDI array multiplier and then assign different combinations of binary values to the dangling internal inputs and some less significant product bits whose logic were eliminated. The usefulness of the proposed approximate array multipliers is analyzed through an image denoising application. One of the approximate array multiplier architectures consistently yields denoised images which closely resembles the denoised images obtained using the accurate array multiplier. Also, it achieves 32.6% reduction in cycle time, 64.2% reduction in area and 26.3% reduction in power on average compared to the optimum accurate QDI array multiplier when considering both return-to-zero and return-to-one handshaking. The accurate and approximate QDI array multipliers were realized using a 32/28-nm CMOS technology. |
| first_indexed | 2024-12-10T23:23:58Z |
| format | Article |
| id | doaj.art-6224a4724a754fe08e70d0c5edfb3ae8 |
| institution | Directory Open Access Journal |
| issn | 2090-4479 |
| language | English |
| last_indexed | 2024-12-10T23:23:58Z |
| publishDate | 2022-05-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Ain Shams Engineering Journal |
| spelling | doaj.art-6224a4724a754fe08e70d0c5edfb3ae82022-12-22T01:29:37ZengElsevierAin Shams Engineering Journal2090-44792022-05-01133101629Quasi delay insensitive implementation of approximate multiplicationPadmanabhan Balasubramanian0Nikos E. Mastorakis1School of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, Singapore; Corresponding author.Department of Industrial Engineering, Technical University of Sofia, 1000 Sofia, BulgariaAsynchronous quasi delay insensitive (QDI) implementation of approximate multiplication is described in this article. We consider the array multiplier architecture for a QDI implementation. We obtain approximate QDI array multipliers by introducing vertical cuts in an accurate QDI array multiplier and then assign different combinations of binary values to the dangling internal inputs and some less significant product bits whose logic were eliminated. The usefulness of the proposed approximate array multipliers is analyzed through an image denoising application. One of the approximate array multiplier architectures consistently yields denoised images which closely resembles the denoised images obtained using the accurate array multiplier. Also, it achieves 32.6% reduction in cycle time, 64.2% reduction in area and 26.3% reduction in power on average compared to the optimum accurate QDI array multiplier when considering both return-to-zero and return-to-one handshaking. The accurate and approximate QDI array multipliers were realized using a 32/28-nm CMOS technology.http://www.sciencedirect.com/science/article/pii/S2090447921003944Approximate computingAsynchronous circuitsArithmetic circuitsDigital circuitsLow powerHigh speed |
| spellingShingle | Padmanabhan Balasubramanian Nikos E. Mastorakis Quasi delay insensitive implementation of approximate multiplication Ain Shams Engineering Journal Approximate computing Asynchronous circuits Arithmetic circuits Digital circuits Low power High speed |
| title | Quasi delay insensitive implementation of approximate multiplication |
| title_full | Quasi delay insensitive implementation of approximate multiplication |
| title_fullStr | Quasi delay insensitive implementation of approximate multiplication |
| title_full_unstemmed | Quasi delay insensitive implementation of approximate multiplication |
| title_short | Quasi delay insensitive implementation of approximate multiplication |
| title_sort | quasi delay insensitive implementation of approximate multiplication |
| topic | Approximate computing Asynchronous circuits Arithmetic circuits Digital circuits Low power High speed |
| url | http://www.sciencedirect.com/science/article/pii/S2090447921003944 |
| work_keys_str_mv | AT padmanabhanbalasubramanian quasidelayinsensitiveimplementationofapproximatemultiplication AT nikosemastorakis quasidelayinsensitiveimplementationofapproximatemultiplication |