Parallel Architecture Design for OpenVX Kernel Image Processing Functions
Although the traditional programmable processors are highly flexible, their processing speed and perfor-mance are inferior to the application specific integrated circuit (ASIC). Image processing is often a diverse, intensive and repetitive operation, so the processor must balance speed, performance...
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| Format: | Article |
| Language: | zho |
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Journal of Computer Engineering and Applications Beijing Co., Ltd., Science Press
2022-07-01
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| Series: | Jisuanji kexue yu tansuo |
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| Online Access: | http://fcst.ceaj.org/fileup/1673-9418/PDF/2012085.pdf |
| _version_ | 1828777828829626368 |
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| author | PAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong |
| author_facet | PAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong |
| author_sort | PAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong |
| collection | DOAJ |
| description | Although the traditional programmable processors are highly flexible, their processing speed and perfor-mance are inferior to the application specific integrated circuit (ASIC). Image processing is often a diverse, intensive and repetitive operation, so the processor must balance speed, performance and flexibility. OpenVX is an open source standard for preprocessing or auxiliary processing of image processing, graph computing and deep learning applications. Aiming at the kernel visual function library of OpenVX 1.3 standard, this paper designs and implements a programmable and extensible OpenVX parallel processor. The architecture adopts an application specific instruction processor (ASIP). After analyzing and comparing the topological characteristics of various interconnection networks, the backbone of the ASIP chooses the hierarchically cross-connected Mesh+ (HCCM+) with outstanding performance, and processing element (PE) is set at network nodes. PE array is constructed to support dynamic configuration, and a parallel processor is designed to realize programmable image processing based on efficient routing and com-munication. The proposed architecture is suitable for data parallel computing and emerging graph computing. The two computing modes can be configured separately or mixed. The kernel visual function and graph computing model are mapped to the parallel processor respectively to verify the two modes and compare the image processing speed under different PE numbers. The results show that OpenVX parallel processor can complete the mapping and linear speedup of kernel functions and high complexity graph calculation model. The average speedup of scheduling 16 PEs to various functions is approximately 15.0375. When implemented on an FPGA board with a 20 nm XCVU440 device, the prototype can run at a frequency of 125 MHz. |
| first_indexed | 2024-12-11T16:30:07Z |
| format | Article |
| id | doaj.art-62bf2d46df7348489a75aefb29ecff5d |
| institution | Directory Open Access Journal |
| issn | 1673-9418 |
| language | zho |
| last_indexed | 2024-12-11T16:30:07Z |
| publishDate | 2022-07-01 |
| publisher | Journal of Computer Engineering and Applications Beijing Co., Ltd., Science Press |
| record_format | Article |
| series | Jisuanji kexue yu tansuo |
| spelling | doaj.art-62bf2d46df7348489a75aefb29ecff5d2022-12-22T00:58:38ZzhoJournal of Computer Engineering and Applications Beijing Co., Ltd., Science PressJisuanji kexue yu tansuo1673-94182022-07-011671570158210.3778/j.issn.1673-9418.2012085Parallel Architecture Design for OpenVX Kernel Image Processing FunctionsPAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong01. School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an 710121, China;2. School of Computer Science & Technology, Xi’an University of Posts & Telecommunications, Xi’an 710121, ChinaAlthough the traditional programmable processors are highly flexible, their processing speed and perfor-mance are inferior to the application specific integrated circuit (ASIC). Image processing is often a diverse, intensive and repetitive operation, so the processor must balance speed, performance and flexibility. OpenVX is an open source standard for preprocessing or auxiliary processing of image processing, graph computing and deep learning applications. Aiming at the kernel visual function library of OpenVX 1.3 standard, this paper designs and implements a programmable and extensible OpenVX parallel processor. The architecture adopts an application specific instruction processor (ASIP). After analyzing and comparing the topological characteristics of various interconnection networks, the backbone of the ASIP chooses the hierarchically cross-connected Mesh+ (HCCM+) with outstanding performance, and processing element (PE) is set at network nodes. PE array is constructed to support dynamic configuration, and a parallel processor is designed to realize programmable image processing based on efficient routing and com-munication. The proposed architecture is suitable for data parallel computing and emerging graph computing. The two computing modes can be configured separately or mixed. The kernel visual function and graph computing model are mapped to the parallel processor respectively to verify the two modes and compare the image processing speed under different PE numbers. The results show that OpenVX parallel processor can complete the mapping and linear speedup of kernel functions and high complexity graph calculation model. The average speedup of scheduling 16 PEs to various functions is approximately 15.0375. When implemented on an FPGA board with a 20 nm XCVU440 device, the prototype can run at a frequency of 125 MHz.http://fcst.ceaj.org/fileup/1673-9418/PDF/2012085.pdf|openvx kernel image processing functions|application specific instruction processor (asip)|parallel processor|hierarchically cross-connected mesh+ (hccm+)|graph calculation model |
| spellingShingle | PAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong Parallel Architecture Design for OpenVX Kernel Image Processing Functions Jisuanji kexue yu tansuo |openvx kernel image processing functions|application specific instruction processor (asip)|parallel processor|hierarchically cross-connected mesh+ (hccm+)|graph calculation model |
| title | Parallel Architecture Design for OpenVX Kernel Image Processing Functions |
| title_full | Parallel Architecture Design for OpenVX Kernel Image Processing Functions |
| title_fullStr | Parallel Architecture Design for OpenVX Kernel Image Processing Functions |
| title_full_unstemmed | Parallel Architecture Design for OpenVX Kernel Image Processing Functions |
| title_short | Parallel Architecture Design for OpenVX Kernel Image Processing Functions |
| title_sort | parallel architecture design for openvx kernel image processing functions |
| topic | |openvx kernel image processing functions|application specific instruction processor (asip)|parallel processor|hierarchically cross-connected mesh+ (hccm+)|graph calculation model |
| url | http://fcst.ceaj.org/fileup/1673-9418/PDF/2012085.pdf |
| work_keys_str_mv | AT panfengruilitaoxinglidongzhanghaocongwuguanzhong parallelarchitecturedesignforopenvxkernelimageprocessingfunctions |