The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length
The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (S...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-11-01
|
| Series: | Nanomaterials |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-4991/13/23/3008 |
| _version_ | 1797399774739038208 |
|---|---|
| author | Priyanka Saha Rudra Sankar Dhar Swagat Nanda Kuleen Kumar Moath Alathbah |
| author_facet | Priyanka Saha Rudra Sankar Dhar Swagat Nanda Kuleen Kumar Moath Alathbah |
| author_sort | Priyanka Saha |
| collection | DOAJ |
| description | The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO<sub>2</sub>) with a stacked gate oxide of 0.5 nm of SiO<sub>2</sub> with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si<sub>3</sub>N<sub>4</sub>, Al<sub>2</sub>O<sub>3</sub>, ZrO<sub>2,</sub> and HfO<sub>2</sub>. It was found that the use of strained silicon and replacing only the SiO<sub>2</sub> device with the stacked SiO<sub>2</sub> and HfO<sub>2</sub> device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. |
| first_indexed | 2024-03-09T01:45:57Z |
| format | Article |
| id | doaj.art-659ced7e50fa4b94b9cf63822cacedea |
| institution | Directory Open Access Journal |
| issn | 2079-4991 |
| language | English |
| last_indexed | 2024-03-09T01:45:57Z |
| publishDate | 2023-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Nanomaterials |
| spelling | doaj.art-659ced7e50fa4b94b9cf63822cacedea2023-12-08T15:22:53ZengMDPI AGNanomaterials2079-49912023-11-011323300810.3390/nano13233008The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel LengthPriyanka Saha0Rudra Sankar Dhar1Swagat Nanda2Kuleen Kumar3Moath Alathbah4Department of ECE, NIT Mizoram, Aizawl 796012, IndiaDepartment of ECE, NIT Mizoram, Aizawl 796012, IndiaDepartment of ECE, NIT Mizoram, Aizawl 796012, IndiaDepartment of ECE, NIT Mizoram, Aizawl 796012, IndiaDepartment of Electrical Engineering, College of Engineering, King Saud University, Riyadh 11451, Saudi ArabiaThe recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO<sub>2</sub>) with a stacked gate oxide of 0.5 nm of SiO<sub>2</sub> with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si<sub>3</sub>N<sub>4</sub>, Al<sub>2</sub>O<sub>3</sub>, ZrO<sub>2,</sub> and HfO<sub>2</sub>. It was found that the use of strained silicon and replacing only the SiO<sub>2</sub> device with the stacked SiO<sub>2</sub> and HfO<sub>2</sub> device was more beneficial to obtain an optimized device with the least leakage and improved drive currents.https://www.mdpi.com/2079-4991/13/23/3008TG FinFETphysical oxide thickness HOI devicestacked high-kSilvaco TCADV<sub>TH</sub>DIBL |
| spellingShingle | Priyanka Saha Rudra Sankar Dhar Swagat Nanda Kuleen Kumar Moath Alathbah The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length Nanomaterials TG FinFET physical oxide thickness HOI device stacked high-k Silvaco TCAD V<sub>TH</sub> DIBL |
| title | The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length |
| title_full | The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length |
| title_fullStr | The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length |
| title_full_unstemmed | The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length |
| title_short | The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length |
| title_sort | optimization and analysis of a triple fin heterostructure on insulator fin field effect transistor with a stacked high k configuration and 10 nm channel length |
| topic | TG FinFET physical oxide thickness HOI device stacked high-k Silvaco TCAD V<sub>TH</sub> DIBL |
| url | https://www.mdpi.com/2079-4991/13/23/3008 |
| work_keys_str_mv | AT priyankasaha theoptimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT rudrasankardhar theoptimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT swagatnanda theoptimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT kuleenkumar theoptimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT moathalathbah theoptimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT priyankasaha optimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT rudrasankardhar optimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT swagatnanda optimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT kuleenkumar optimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength AT moathalathbah optimizationandanalysisofatriplefinheterostructureoninsulatorfinfieldeffecttransistorwithastackedhighkconfigurationand10nmchannellength |