Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber
This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feed...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-05-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/12/11/5305 |
| _version_ | 1797494321195253760 |
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| author | Tuy Tan Nguyen Sungjae Kim Yongjun Eom Hanho Lee |
| author_facet | Tuy Tan Nguyen Sungjae Kim Yongjun Eom Hanho Lee |
| author_sort | Tuy Tan Nguyen |
| collection | DOAJ |
| description | This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feedback number theoretic transform multiplier dedicating for Kyber parameter set and deploying this multiplier in the Kyber architecture, the key generation, encryption, and decryption operations are accelerated substantially. Furthermore, the proposed architecture offers the best value of area-time product in comparison with existing approaches. The implementation results on Xilinx Vivado targeted for Virtex-7 FPGA board demonstrate that the proposed Kyber cryptoprocessor completes encryption and decryption operations in approximately 57.5 μs at the highest frequency of 226 MHz. Furthermore, the area-time product value when using the proposed Kyber architecture is improved by at least twofold compared with existing architectures. |
| first_indexed | 2024-03-10T01:32:35Z |
| format | Article |
| id | doaj.art-65e2955b8935452a8361c8c618890e13 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-10T01:32:35Z |
| publishDate | 2022-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-65e2955b8935452a8361c8c618890e132023-11-23T13:39:24ZengMDPI AGApplied Sciences2076-34172022-05-011211530510.3390/app12115305Area-Time Efficient Hardware Architecture for CRYSTALS-KyberTuy Tan Nguyen0Sungjae Kim1Yongjun Eom2Hanho Lee3Department of Information and Communication Engineering, Inha University, Incheon 22212, KoreaDepartment of Information and Communication Engineering, Inha University, Incheon 22212, KoreaDepartment of Information and Communication Engineering, Inha University, Incheon 22212, KoreaDepartment of Information and Communication Engineering, Inha University, Incheon 22212, KoreaThis paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feedback number theoretic transform multiplier dedicating for Kyber parameter set and deploying this multiplier in the Kyber architecture, the key generation, encryption, and decryption operations are accelerated substantially. Furthermore, the proposed architecture offers the best value of area-time product in comparison with existing approaches. The implementation results on Xilinx Vivado targeted for Virtex-7 FPGA board demonstrate that the proposed Kyber cryptoprocessor completes encryption and decryption operations in approximately 57.5 μs at the highest frequency of 226 MHz. Furthermore, the area-time product value when using the proposed Kyber architecture is improved by at least twofold compared with existing architectures.https://www.mdpi.com/2076-3417/12/11/5305CRYSTALS-Kyberdecryptionencryptionnumber theoretic transform (NTT)polynomial multiplierpost-quantum cryptography |
| spellingShingle | Tuy Tan Nguyen Sungjae Kim Yongjun Eom Hanho Lee Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber Applied Sciences CRYSTALS-Kyber decryption encryption number theoretic transform (NTT) polynomial multiplier post-quantum cryptography |
| title | Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber |
| title_full | Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber |
| title_fullStr | Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber |
| title_full_unstemmed | Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber |
| title_short | Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber |
| title_sort | area time efficient hardware architecture for crystals kyber |
| topic | CRYSTALS-Kyber decryption encryption number theoretic transform (NTT) polynomial multiplier post-quantum cryptography |
| url | https://www.mdpi.com/2076-3417/12/11/5305 |
| work_keys_str_mv | AT tuytannguyen areatimeefficienthardwarearchitectureforcrystalskyber AT sungjaekim areatimeefficienthardwarearchitectureforcrystalskyber AT yongjuneom areatimeefficienthardwarearchitectureforcrystalskyber AT hanholee areatimeefficienthardwarearchitectureforcrystalskyber |