A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS
In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is ap...
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| Format: | Article |
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MDPI AG
2020-05-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/5/802 |
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| author | Heng You Jia Yuan Weidi Tang Zenghui Yu Shushan Qiao |
| author_facet | Heng You Jia Yuan Weidi Tang Zenghui Yu Shushan Qiao |
| author_sort | Heng You |
| collection | DOAJ |
| description | In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm<sup>2</sup> (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V. |
| first_indexed | 2024-03-10T19:51:32Z |
| format | Article |
| id | doaj.art-669adca59b2048d9903db24afddc0cfc |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T19:51:32Z |
| publishDate | 2020-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-669adca59b2048d9903db24afddc0cfc2023-11-20T00:21:02ZengMDPI AGElectronics2079-92922020-05-019580210.3390/electronics9050802A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOSHeng You0Jia Yuan1Weidi Tang2Zenghui Yu3Shushan Qiao4Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaDepartment of Electronic Science and Technology, University of Science and Technology of China, Hefei 230026, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaIn this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm<sup>2</sup> (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.https://www.mdpi.com/2079-9292/9/5/802low-powerhigh-speedflip-flopsense-amplifierMTCMOS |
| spellingShingle | Heng You Jia Yuan Weidi Tang Zenghui Yu Shushan Qiao A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS Electronics low-power high-speed flip-flop sense-amplifier MTCMOS |
| title | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS |
| title_full | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS |
| title_fullStr | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS |
| title_full_unstemmed | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS |
| title_short | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS |
| title_sort | low power high speed sense amplifier based flip flop in 55 nm mtcmos |
| topic | low-power high-speed flip-flop sense-amplifier MTCMOS |
| url | https://www.mdpi.com/2079-9292/9/5/802 |
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