Algorithm for matching physical and logical addressing in memory chips using laser sources
The paper presents the developed algorithm for correlating the physical and logical addressing in memory chips using laser radiation sources to determine the nature of failures in radiation tests. A variant of the hardware-software implementation of the algorithm is proposed, key software tools are...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Joint Stock Company "Experimental Scientific and Production Association SPELS
2020-09-01
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| Series: | Безопасность информационных технологий |
| Subjects: | |
| Online Access: | https://bit.mephi.ru/index.php/bit/article/view/1291 |
| Summary: | The paper presents the developed algorithm for correlating the physical and logical addressing in memory chips using laser radiation sources to determine the nature of failures in radiation tests. A variant of the hardware-software implementation of the algorithm is proposed, key software tools are presented. The algorithm was tested using the focused laser facility with the ability to irradiate a separate memory cell. The patterns of location of the memory cells in single memory block were obtained, necessary to compose the full correlation between the physical and logical addressing. The main experimental results of the algorithm approbation are shown, which confirm the possibility of developing the tool for visualizing the map of failures with one-bit precision. The adaptation of the tool for analyzing the hardness of a static random-access memory (SRAM) IC under pulsed ionizing radiation is presented. |
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| ISSN: | 2074-7128 2074-7136 |