Formation techniques for upper active channel in monolithic 3D integration: an overview
Abstract The concept of three-dimensional stacking of device layers has attracted significant attention with the increasing difficulty in scaling down devices. Monolithic 3D (M3D) integration provides a notable benefit in achieving a higher connection density between upper and lower device layers th...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2024-01-01
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| Series: | Nano Convergence |
| Subjects: | |
| Online Access: | https://doi.org/10.1186/s40580-023-00411-4 |
| _version_ | 1827326514396397568 |
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| author | An Hoang-Thuy Nguyen Manh-Cuong Nguyen Anh-Duy Nguyen Seung Joon Jeon Noh-Hwal Park Jeong-Hwan Lee Rino Choi |
| author_facet | An Hoang-Thuy Nguyen Manh-Cuong Nguyen Anh-Duy Nguyen Seung Joon Jeon Noh-Hwal Park Jeong-Hwan Lee Rino Choi |
| author_sort | An Hoang-Thuy Nguyen |
| collection | DOAJ |
| description | Abstract The concept of three-dimensional stacking of device layers has attracted significant attention with the increasing difficulty in scaling down devices. Monolithic 3D (M3D) integration provides a notable benefit in achieving a higher connection density between upper and lower device layers than through-via-silicon. Nevertheless, the practical implementation of M3D integration into commercial production faces several technological challenges. Developing an upper active channel layer for device fabrication is the primary challenge in M3D integration. The difficulty arises from the thermal budget limitation for the upper channel process because a high thermal budget process may degrade the device layers below. This paper provides an overview of the potential technologies for forming active channel layers in the upper device layers of M3D integration, particularly for complementary metal-oxide-semiconductor devices and digital circuits. Techniques are for polysilicon, single crystal silicon, and alternative channels, which can solve the temperature issue for the top layer process. |
| first_indexed | 2024-03-07T14:46:41Z |
| format | Article |
| id | doaj.art-6715487770bd4c1ca5eef38c9a8113e2 |
| institution | Directory Open Access Journal |
| issn | 2196-5404 |
| language | English |
| last_indexed | 2024-03-07T14:46:41Z |
| publishDate | 2024-01-01 |
| publisher | SpringerOpen |
| record_format | Article |
| series | Nano Convergence |
| spelling | doaj.art-6715487770bd4c1ca5eef38c9a8113e22024-03-05T19:56:35ZengSpringerOpenNano Convergence2196-54042024-01-0111111510.1186/s40580-023-00411-4Formation techniques for upper active channel in monolithic 3D integration: an overviewAn Hoang-Thuy Nguyen0Manh-Cuong Nguyen1Anh-Duy Nguyen2Seung Joon Jeon3Noh-Hwal Park4Jeong-Hwan Lee5Rino Choi63D Convergence Center at Inha University3D Convergence Center at Inha UniversityDepartment of Materials Science and Engineering, Inha University3D Convergence Center at Inha University3D Convergence Center at Inha University3D Convergence Center at Inha University3D Convergence Center at Inha UniversityAbstract The concept of three-dimensional stacking of device layers has attracted significant attention with the increasing difficulty in scaling down devices. Monolithic 3D (M3D) integration provides a notable benefit in achieving a higher connection density between upper and lower device layers than through-via-silicon. Nevertheless, the practical implementation of M3D integration into commercial production faces several technological challenges. Developing an upper active channel layer for device fabrication is the primary challenge in M3D integration. The difficulty arises from the thermal budget limitation for the upper channel process because a high thermal budget process may degrade the device layers below. This paper provides an overview of the potential technologies for forming active channel layers in the upper device layers of M3D integration, particularly for complementary metal-oxide-semiconductor devices and digital circuits. Techniques are for polysilicon, single crystal silicon, and alternative channels, which can solve the temperature issue for the top layer process.https://doi.org/10.1186/s40580-023-00411-4Monolithic 3DThermal budget limitationUpper layerTechniques |
| spellingShingle | An Hoang-Thuy Nguyen Manh-Cuong Nguyen Anh-Duy Nguyen Seung Joon Jeon Noh-Hwal Park Jeong-Hwan Lee Rino Choi Formation techniques for upper active channel in monolithic 3D integration: an overview Nano Convergence Monolithic 3D Thermal budget limitation Upper layer Techniques |
| title | Formation techniques for upper active channel in monolithic 3D integration: an overview |
| title_full | Formation techniques for upper active channel in monolithic 3D integration: an overview |
| title_fullStr | Formation techniques for upper active channel in monolithic 3D integration: an overview |
| title_full_unstemmed | Formation techniques for upper active channel in monolithic 3D integration: an overview |
| title_short | Formation techniques for upper active channel in monolithic 3D integration: an overview |
| title_sort | formation techniques for upper active channel in monolithic 3d integration an overview |
| topic | Monolithic 3D Thermal budget limitation Upper layer Techniques |
| url | https://doi.org/10.1186/s40580-023-00411-4 |
| work_keys_str_mv | AT anhoangthuynguyen formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT manhcuongnguyen formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT anhduynguyen formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT seungjoonjeon formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT nohhwalpark formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT jeonghwanlee formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview AT rinochoi formationtechniquesforupperactivechannelinmonolithic3dintegrationanoverview |