Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL pr...

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Bibliographic Details
Main Authors: Xuanjie Liu, Qingqing Sun, Yiping Huang, Zheng Chen, Guoan Liu, David Wei Zhang
Format: Article
Language:English
Published: MDPI AG 2021-09-01
Series:Electronics
Subjects:
TSV
via-middle
leakage current
bulk micro defect
stress
Online Access:https://www.mdpi.com/2079-9292/10/19/2370

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