Redundant Hardware Components for ASIC. RTL Model and Synthesys
Redundancy is a very popular and effective method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different wa...
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| Format: | Article |
| Language: | English |
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FRUCT
2018-05-01
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| Series: | Proceedings of the XXth Conference of Open Innovations Association FRUCT |
| Subjects: | |
| Online Access: | https://fruct.org/publications/abstract22/files/Roz.pdf |
| _version_ | 1818877551311847424 |
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| author | Valentin Rozanov Yuriy Sheynin Elena Suvorova |
| author_facet | Valentin Rozanov Yuriy Sheynin Elena Suvorova |
| author_sort | Valentin Rozanov |
| collection | DOAJ |
| description | Redundancy is a very popular and effective method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection. From hardware design point of view (ASIC design especially) redundancy means area and power increasing. It is very important to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation and additional efforts that need to be done during hardware design flow to get redundant component with fault tolerant mechanism. |
| first_indexed | 2024-12-19T14:00:05Z |
| format | Article |
| id | doaj.art-67fc686f5e7145a0bfceb4e3d90e41eb |
| institution | Directory Open Access Journal |
| issn | 2305-7254 2343-0737 |
| language | English |
| last_indexed | 2024-12-19T14:00:05Z |
| publishDate | 2018-05-01 |
| publisher | FRUCT |
| record_format | Article |
| series | Proceedings of the XXth Conference of Open Innovations Association FRUCT |
| spelling | doaj.art-67fc686f5e7145a0bfceb4e3d90e41eb2022-12-21T20:18:29ZengFRUCTProceedings of the XXth Conference of Open Innovations Association FRUCT2305-72542343-07372018-05-0142622378384Redundant Hardware Components for ASIC. RTL Model and SynthesysValentin Rozanov0Yuriy Sheynin1Elena Suvorova2Saint-Petersburg State University of Aerospace Instrumentation, Saint-Petersburg, Russian FederationSaint-Petersburg State University of Aerospace Instrumentation, Saint-Petersburg, Russian FederationSaint-Petersburg State University of Aerospace Instrumentation, Saint-Petersburg, Russian FederationRedundancy is a very popular and effective method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection. From hardware design point of view (ASIC design especially) redundancy means area and power increasing. It is very important to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation and additional efforts that need to be done during hardware design flow to get redundant component with fault tolerant mechanism.https://fruct.org/publications/abstract22/files/Roz.pdfsynthesisASICredundancyRTLhardware desing flow |
| spellingShingle | Valentin Rozanov Yuriy Sheynin Elena Suvorova Redundant Hardware Components for ASIC. RTL Model and Synthesys Proceedings of the XXth Conference of Open Innovations Association FRUCT synthesis ASIC redundancy RTL hardware desing flow |
| title | Redundant Hardware Components for ASIC. RTL Model and Synthesys |
| title_full | Redundant Hardware Components for ASIC. RTL Model and Synthesys |
| title_fullStr | Redundant Hardware Components for ASIC. RTL Model and Synthesys |
| title_full_unstemmed | Redundant Hardware Components for ASIC. RTL Model and Synthesys |
| title_short | Redundant Hardware Components for ASIC. RTL Model and Synthesys |
| title_sort | redundant hardware components for asic rtl model and synthesys |
| topic | synthesis ASIC redundancy RTL hardware desing flow |
| url | https://fruct.org/publications/abstract22/files/Roz.pdf |
| work_keys_str_mv | AT valentinrozanov redundanthardwarecomponentsforasicrtlmodelandsynthesys AT yuriysheynin redundanthardwarecomponentsforasicrtlmodelandsynthesys AT elenasuvorova redundanthardwarecomponentsforasicrtlmodelandsynthesys |