A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration
Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chip...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-12-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/13/1/37 |
| _version_ | 1797358938120781824 |
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| author | Meng Liu Yunfei Wang Shuai Li |
| author_facet | Meng Liu Yunfei Wang Shuai Li |
| author_sort | Meng Liu |
| collection | DOAJ |
| description | Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption. |
| first_indexed | 2024-03-08T15:09:24Z |
| format | Article |
| id | doaj.art-6cdfd876c04d409a83c3d93bca2865a1 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-08T15:09:24Z |
| publishDate | 2023-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-6cdfd876c04d409a83c3d93bca2865a12024-01-10T14:54:12ZengMDPI AGElectronics2079-92922023-12-011313710.3390/electronics13010037A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU AccelerationMeng Liu0Yunfei Wang1Shuai Li2Faculty of Information Technology, Beijing University of Technology, Beijing 100025, ChinaFaculty of Information Technology, Beijing University of Technology, Beijing 100025, ChinaFaculty of Information Technology, Beijing University of Technology, Beijing 100025, ChinaField Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.https://www.mdpi.com/2079-9292/13/1/37FPGAEDApackingplacementGPU accelerationmethodology |
| spellingShingle | Meng Liu Yunfei Wang Shuai Li A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration Electronics FPGA EDA packing placement GPU acceleration methodology |
| title | A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration |
| title_full | A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration |
| title_fullStr | A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration |
| title_full_unstemmed | A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration |
| title_short | A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration |
| title_sort | field programmable gate array placement methodology for netlist level circuits with gpu acceleration |
| topic | FPGA EDA packing placement GPU acceleration methodology |
| url | https://www.mdpi.com/2079-9292/13/1/37 |
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