A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chip...

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Bibliographic Details
Main Authors: Meng Liu, Yunfei Wang, Shuai Li
Format: Article
Language:English
Published: MDPI AG 2023-12-01
Series:Electronics
Subjects:
FPGA
EDA
packing
placement
GPU acceleration
methodology
Online Access:https://www.mdpi.com/2079-9292/13/1/37

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