Functional Devices from Bottom-Up Silicon Nanowires: A Review
This paper summarizes some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting nanowires in functional devices, from single nanowires to large assemblies of nanowires such as nanonets (two-dimensional...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-03-01
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| Series: | Nanomaterials |
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| Online Access: | https://www.mdpi.com/2079-4991/12/7/1043 |
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| author | Tabassom Arjmand Maxime Legallais Thi Thu Thuy Nguyen Pauline Serre Monica Vallejo-Perez Fanny Morisot Bassem Salem Céline Ternon |
| author_facet | Tabassom Arjmand Maxime Legallais Thi Thu Thuy Nguyen Pauline Serre Monica Vallejo-Perez Fanny Morisot Bassem Salem Céline Ternon |
| author_sort | Tabassom Arjmand |
| collection | DOAJ |
| description | This paper summarizes some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting nanowires in functional devices, from single nanowires to large assemblies of nanowires such as nanonets (two-dimensional arrays of randomly oriented nanowires), are briefly reviewed. Subsequently, the main properties of nanowires are discussed followed by those of nanonets that benefit from the large numbers of nanowires involved. After describing the main techniques used for the growth of nanowires, in the context of functional device fabrication, the different techniques used for nanowire manipulation are largely presented as they constitute one of the first fundamental steps that allows the nanowire positioning necessary to start the integration process. The advantages and disadvantages of each of these manipulation techniques are discussed. Then, the main families of nanowire-based transistors are presented; their most common integration routes and the electrical performance of the resulting devices are also presented and compared in order to highlight the relevance of these different geometries. Because they can be bottlenecks, the key technological elements necessary for the integration of silicon nanowires are detailed: the sintering technique, the importance of surface and interface engineering, and the key role of silicidation for good device performance. Finally the main application areas for these silicon nanowire devices are reviewed. |
| first_indexed | 2024-03-09T11:34:57Z |
| format | Article |
| id | doaj.art-6e17149fe929441f9fefafec4da2f392 |
| institution | Directory Open Access Journal |
| issn | 2079-4991 |
| language | English |
| last_indexed | 2024-03-09T11:34:57Z |
| publishDate | 2022-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Nanomaterials |
| spelling | doaj.art-6e17149fe929441f9fefafec4da2f3922023-11-30T23:43:32ZengMDPI AGNanomaterials2079-49912022-03-01127104310.3390/nano12071043Functional Devices from Bottom-Up Silicon Nanowires: A ReviewTabassom Arjmand0Maxime Legallais1Thi Thu Thuy Nguyen2Pauline Serre3Monica Vallejo-Perez4Fanny Morisot5Bassem Salem6Céline Ternon7Univ. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, CEA/LETI-Minatec, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LTM, F-38000 Grenoble, FranceUniv. Grenoble Alpes, CNRS, Grenoble INP (Institute of Engineering Univ. Grenoble Alpes), LMGP, F-38000 Grenoble, FranceThis paper summarizes some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting nanowires in functional devices, from single nanowires to large assemblies of nanowires such as nanonets (two-dimensional arrays of randomly oriented nanowires), are briefly reviewed. Subsequently, the main properties of nanowires are discussed followed by those of nanonets that benefit from the large numbers of nanowires involved. After describing the main techniques used for the growth of nanowires, in the context of functional device fabrication, the different techniques used for nanowire manipulation are largely presented as they constitute one of the first fundamental steps that allows the nanowire positioning necessary to start the integration process. The advantages and disadvantages of each of these manipulation techniques are discussed. Then, the main families of nanowire-based transistors are presented; their most common integration routes and the electrical performance of the resulting devices are also presented and compared in order to highlight the relevance of these different geometries. Because they can be bottlenecks, the key technological elements necessary for the integration of silicon nanowires are detailed: the sintering technique, the importance of surface and interface engineering, and the key role of silicidation for good device performance. Finally the main application areas for these silicon nanowire devices are reviewed.https://www.mdpi.com/2079-4991/12/7/1043nanowiresnanonetstransistorintegration processsilicon |
| spellingShingle | Tabassom Arjmand Maxime Legallais Thi Thu Thuy Nguyen Pauline Serre Monica Vallejo-Perez Fanny Morisot Bassem Salem Céline Ternon Functional Devices from Bottom-Up Silicon Nanowires: A Review Nanomaterials nanowires nanonets transistor integration process silicon |
| title | Functional Devices from Bottom-Up Silicon Nanowires: A Review |
| title_full | Functional Devices from Bottom-Up Silicon Nanowires: A Review |
| title_fullStr | Functional Devices from Bottom-Up Silicon Nanowires: A Review |
| title_full_unstemmed | Functional Devices from Bottom-Up Silicon Nanowires: A Review |
| title_short | Functional Devices from Bottom-Up Silicon Nanowires: A Review |
| title_sort | functional devices from bottom up silicon nanowires a review |
| topic | nanowires nanonets transistor integration process silicon |
| url | https://www.mdpi.com/2079-4991/12/7/1043 |
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