Improved Floating Point Multiplier Design based on Canonical Sign Digit
Improved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Universitas Indonesia
2014-01-01
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| Series: | International Journal of Technology |
| Subjects: | |
| Online Access: | http://ijtech.eng.ui.ac.id/article/view/1286 |
| _version_ | 1828075069993123840 |
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| author | P. Saha P. Bhattacharyya A. Dandapat |
| author_facet | P. Saha P. Bhattacharyya A. Dandapat |
| author_sort | P. Saha |
| collection | DOAJ |
| description | Improved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches were used for the addition of partial products in constant time without carry propagation and independent of operands. The functionality of these circuits was checked and performance parameters, such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. Implementation methodology ensures the stage reduction for floating point multiplier, hence substantial reduction in propagation delay compared with B.W.’s methodology, has been investigated. Implementation result offered propagation delay of the single precision floating point multiplier was only ~14.7ns propagation delay while the power consumption of the same was ~23.7mW. Almost ~40% improvement in speed from earlier reported FP multiplier, e.g. B.W implementation methodology, the best architecture reported so far, has been achieved. |
| first_indexed | 2024-04-11T01:52:01Z |
| format | Article |
| id | doaj.art-706b9549f12641998c7e54dddcb072a8 |
| institution | Directory Open Access Journal |
| issn | 2086-9614 2087-2100 |
| language | English |
| last_indexed | 2024-04-11T01:52:01Z |
| publishDate | 2014-01-01 |
| publisher | Universitas Indonesia |
| record_format | Article |
| series | International Journal of Technology |
| spelling | doaj.art-706b9549f12641998c7e54dddcb072a82023-01-03T06:05:06ZengUniversitas IndonesiaInternational Journal of Technology2086-96142087-21002014-01-0151223110.14716/ijtech.v5i1.12861286Improved Floating Point Multiplier Design based on Canonical Sign DigitP. Saha0P. Bhattacharyya1A. Dandapat2Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, IndiaDepartment of Electronics and Telecommunication Engineering, Bengal Engineering and Science University. Shibpur, Howrah-711103, IndiaDepartment of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, IndiaImproved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches were used for the addition of partial products in constant time without carry propagation and independent of operands. The functionality of these circuits was checked and performance parameters, such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. Implementation methodology ensures the stage reduction for floating point multiplier, hence substantial reduction in propagation delay compared with B.W.’s methodology, has been investigated. Implementation result offered propagation delay of the single precision floating point multiplier was only ~14.7ns propagation delay while the power consumption of the same was ~23.7mW. Almost ~40% improvement in speed from earlier reported FP multiplier, e.g. B.W implementation methodology, the best architecture reported so far, has been achieved.http://ijtech.eng.ui.ac.id/article/view/1286Baugh-Wooley (B.W) multiplier, CSD adder, CSD multiplier, High Speed |
| spellingShingle | P. Saha P. Bhattacharyya A. Dandapat Improved Floating Point Multiplier Design based on Canonical Sign Digit International Journal of Technology Baugh-Wooley (B.W) multiplier, CSD adder, CSD multiplier, High Speed |
| title | Improved Floating Point Multiplier Design based on Canonical Sign Digit |
| title_full | Improved Floating Point Multiplier Design based on Canonical Sign Digit |
| title_fullStr | Improved Floating Point Multiplier Design based on Canonical Sign Digit |
| title_full_unstemmed | Improved Floating Point Multiplier Design based on Canonical Sign Digit |
| title_short | Improved Floating Point Multiplier Design based on Canonical Sign Digit |
| title_sort | improved floating point multiplier design based on canonical sign digit |
| topic | Baugh-Wooley (B.W) multiplier, CSD adder, CSD multiplier, High Speed |
| url | http://ijtech.eng.ui.ac.id/article/view/1286 |
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