Fault Tolerant Digital Data-Path Design via Control Feedback Loops
In this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults....
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-10-01
|
| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/9/10/1721 |
| _version_ | 1797550526310645760 |
|---|---|
| author | Oana Boncalo Alexandru Amaricai Zsófia Lendek |
| author_facet | Oana Boncalo Alexandru Amaricai Zsófia Lendek |
| author_sort | Oana Boncalo |
| collection | DOAJ |
| description | In this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults. Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output. The correction loops apply correction factors to selected data-path registers from blocks that have their execution rewinded. We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy. For Field Programmable Gate Array (FPGA) technology, the solution we propose uses 30% less slices with respect to Triple Modular Redundancy (TMR), while having a third less digital signal processing blocks. Simulation results show that our approach improves the reliability and error detection. |
| first_indexed | 2024-03-10T15:30:35Z |
| format | Article |
| id | doaj.art-709ff6a540d1458a8f2a4bafd5a5f055 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T15:30:35Z |
| publishDate | 2020-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-709ff6a540d1458a8f2a4bafd5a5f0552023-11-20T17:41:44ZengMDPI AGElectronics2079-92922020-10-01910172110.3390/electronics9101721Fault Tolerant Digital Data-Path Design via Control Feedback LoopsOana Boncalo0Alexandru Amaricai1Zsófia Lendek2Department of Computers and Information Technology, Universitatea Politehnica Timisoara, Piata Victoriei 2, 300006 Timisoara, RomaniaDepartment of Computers and Information Technology, Universitatea Politehnica Timisoara, Piata Victoriei 2, 300006 Timisoara, RomaniaDepartment of Automation, Technical University of Cluj-Napoca, Memorandumului 28, 400114 Cluj-Napoca, RomaniaIn this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults. Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output. The correction loops apply correction factors to selected data-path registers from blocks that have their execution rewinded. We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy. For Field Programmable Gate Array (FPGA) technology, the solution we propose uses 30% less slices with respect to Triple Modular Redundancy (TMR), while having a third less digital signal processing blocks. Simulation results show that our approach improves the reliability and error detection.https://www.mdpi.com/2079-9292/9/10/1721fault tolerancereliabilityarithmetic data-pathFPGAcontrol engineeringfeedback controller |
| spellingShingle | Oana Boncalo Alexandru Amaricai Zsófia Lendek Fault Tolerant Digital Data-Path Design via Control Feedback Loops Electronics fault tolerance reliability arithmetic data-path FPGA control engineering feedback controller |
| title | Fault Tolerant Digital Data-Path Design via Control Feedback Loops |
| title_full | Fault Tolerant Digital Data-Path Design via Control Feedback Loops |
| title_fullStr | Fault Tolerant Digital Data-Path Design via Control Feedback Loops |
| title_full_unstemmed | Fault Tolerant Digital Data-Path Design via Control Feedback Loops |
| title_short | Fault Tolerant Digital Data-Path Design via Control Feedback Loops |
| title_sort | fault tolerant digital data path design via control feedback loops |
| topic | fault tolerance reliability arithmetic data-path FPGA control engineering feedback controller |
| url | https://www.mdpi.com/2079-9292/9/10/1721 |
| work_keys_str_mv | AT oanaboncalo faulttolerantdigitaldatapathdesignviacontrolfeedbackloops AT alexandruamaricai faulttolerantdigitaldatapathdesignviacontrolfeedbackloops AT zsofialendek faulttolerantdigitaldatapathdesignviacontrolfeedbackloops |