Sidewall Slope Control of InP Via Holes for 3D Integration
This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO<sub>2</sub> layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher oper...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-01-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/12/1/89 |
| _version_ | 1797410828054429696 |
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| author | Jongwon Lee Kilsun Roh Sung-Kyu Lim Youngsu Kim |
| author_facet | Jongwon Lee Kilsun Roh Sung-Kyu Lim Youngsu Kim |
| author_sort | Jongwon Lee |
| collection | DOAJ |
| description | This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO<sub>2</sub> layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl<sub>2</sub>/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO<sub>2</sub> layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO<sub>2</sub> layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO<sub>2</sub> selectivity with RF power. |
| first_indexed | 2024-03-09T04:35:54Z |
| format | Article |
| id | doaj.art-721d903c64cb41668e61ff9146767d0e |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-09T04:35:54Z |
| publishDate | 2021-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-721d903c64cb41668e61ff9146767d0e2023-12-03T13:28:12ZengMDPI AGMicromachines2072-666X2021-01-011218910.3390/mi12010089Sidewall Slope Control of InP Via Holes for 3D IntegrationJongwon Lee0Kilsun Roh1Sung-Kyu Lim2Youngsu Kim3Division of System IC Development, National Nanofab Center, Daejeon 34141, KoreaDivision of Nano Patterning Process, National Nanofab Center, Daejeon 34141, KoreaDivision of Nano Thin Film Process, National Nanofab Center, Daejeon 34141, KoreaDivision of System IC Development, National Nanofab Center, Daejeon 34141, KoreaThis is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO<sub>2</sub> layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl<sub>2</sub>/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO<sub>2</sub> layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO<sub>2</sub> layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO<sub>2</sub> selectivity with RF power.https://www.mdpi.com/2072-666X/12/1/89InPvia hole3D integrationthrough substrate via (TSV) |
| spellingShingle | Jongwon Lee Kilsun Roh Sung-Kyu Lim Youngsu Kim Sidewall Slope Control of InP Via Holes for 3D Integration Micromachines InP via hole 3D integration through substrate via (TSV) |
| title | Sidewall Slope Control of InP Via Holes for 3D Integration |
| title_full | Sidewall Slope Control of InP Via Holes for 3D Integration |
| title_fullStr | Sidewall Slope Control of InP Via Holes for 3D Integration |
| title_full_unstemmed | Sidewall Slope Control of InP Via Holes for 3D Integration |
| title_short | Sidewall Slope Control of InP Via Holes for 3D Integration |
| title_sort | sidewall slope control of inp via holes for 3d integration |
| topic | InP via hole 3D integration through substrate via (TSV) |
| url | https://www.mdpi.com/2072-666X/12/1/89 |
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