Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook
The synchronous design paradigm dominates today’s semiconductor industry. However, this clocked approach is facing major challenges with today’s high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related iss...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9840347/ |
| _version_ | 1818016000981860352 |
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| author | Danylo Khodosevych Ashiq A. Sakib |
| author_facet | Danylo Khodosevych Ashiq A. Sakib |
| author_sort | Danylo Khodosevych |
| collection | DOAJ |
| description | The synchronous design paradigm dominates today’s semiconductor industry. However, this clocked approach is facing major challenges with today’s high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions. |
| first_indexed | 2024-04-14T07:07:12Z |
| format | Article |
| id | doaj.art-72500e921fbc45ea8d71d5632a747b5e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-14T07:07:12Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-72500e921fbc45ea8d71d5632a747b5e2022-12-22T02:06:33ZengIEEEIEEE Access2169-35362022-01-0110786507866610.1109/ACCESS.2022.31940289840347Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and OutlookDanylo Khodosevych0Ashiq A. Sakib1https://orcid.org/0000-0001-7985-2449Department of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, FL, USADepartment of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, FL, USAThe synchronous design paradigm dominates today’s semiconductor industry. However, this clocked approach is facing major challenges with today’s high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.https://ieeexplore.ieee.org/document/9840347/Asynchronous circuitsdesign automationlogic optimizationnull convention logictestingverification |
| spellingShingle | Danylo Khodosevych Ashiq A. Sakib Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook IEEE Access Asynchronous circuits design automation logic optimization null convention logic testing verification |
| title | Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook |
| title_full | Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook |
| title_fullStr | Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook |
| title_full_unstemmed | Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook |
| title_short | Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook |
| title_sort | evolution of null convention logic based asynchronous paradigm an overview and outlook |
| topic | Asynchronous circuits design automation logic optimization null convention logic testing verification |
| url | https://ieeexplore.ieee.org/document/9840347/ |
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