Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Different from the deep neural network (DNN) inference process, the training process produces a huge amount of intermediate data to compute the new weights of the network. Generally, the on-chip global buffer (e.g., SRAM cache) has limited capacity because of its low memory density; therefore, off-c...

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Bibliographic Details
Main Authors: Wonbo Shim, Shimeng Yu
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Subjects:
3-D NAND
compute-in-memory (CIM)
deep neural network (DNN)
ferroelectric transistor
on-chip training accelerator
Online Access:https://ieeexplore.ieee.org/document/9350264/

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