DMA controller design based on SHA-1 dual channel improvement algorithm
In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and mu...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
AIP Publishing LLC
2023-11-01
|
| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/5.0179525 |
| _version_ | 1827595830387802112 |
|---|---|
| author | Wei Wang Cong He Jia Qi Shi |
| author_facet | Wei Wang Cong He Jia Qi Shi |
| author_sort | Wei Wang |
| collection | DOAJ |
| description | In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects. |
| first_indexed | 2024-03-09T03:00:05Z |
| format | Article |
| id | doaj.art-73c09a26f9e84a4db57ba8b81630ed20 |
| institution | Directory Open Access Journal |
| issn | 2158-3226 |
| language | English |
| last_indexed | 2024-03-09T03:00:05Z |
| publishDate | 2023-11-01 |
| publisher | AIP Publishing LLC |
| record_format | Article |
| series | AIP Advances |
| spelling | doaj.art-73c09a26f9e84a4db57ba8b81630ed202023-12-04T17:18:29ZengAIP Publishing LLCAIP Advances2158-32262023-11-011311115127115127-1110.1063/5.0179525DMA controller design based on SHA-1 dual channel improvement algorithmWei Wang0Cong He1Jia Qi Shi2Jiangsu Province Engineering Research Center of Integrated Circuit Reliability Technology and Testing System, Wuxi University, Wuxi, ChinaSchool of Electronic and Information Engineering, Nanjing University of Information Science and Technology, Nanjing, ChinaSchool of Atmospheric Physics, Nanjing University of Information Science and Technology, Nanjing, ChinaIn order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects.http://dx.doi.org/10.1063/5.0179525 |
| spellingShingle | Wei Wang Cong He Jia Qi Shi DMA controller design based on SHA-1 dual channel improvement algorithm AIP Advances |
| title | DMA controller design based on SHA-1 dual channel improvement algorithm |
| title_full | DMA controller design based on SHA-1 dual channel improvement algorithm |
| title_fullStr | DMA controller design based on SHA-1 dual channel improvement algorithm |
| title_full_unstemmed | DMA controller design based on SHA-1 dual channel improvement algorithm |
| title_short | DMA controller design based on SHA-1 dual channel improvement algorithm |
| title_sort | dma controller design based on sha 1 dual channel improvement algorithm |
| url | http://dx.doi.org/10.1063/5.0179525 |
| work_keys_str_mv | AT weiwang dmacontrollerdesignbasedonsha1dualchannelimprovementalgorithm AT conghe dmacontrollerdesignbasedonsha1dualchannelimprovementalgorithm AT jiaqishi dmacontrollerdesignbasedonsha1dualchannelimprovementalgorithm |