Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm
System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9964215/ |
| _version_ | 1811205558281175040 |
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| author | Gokul Chandrasekaran Neelam Sanjeev Kumar P. R. Karthikeyan K. Vanchinathan Neeraj Priyadarshi Bhekisipho Twala |
| author_facet | Gokul Chandrasekaran Neelam Sanjeev Kumar P. R. Karthikeyan K. Vanchinathan Neeraj Priyadarshi Bhekisipho Twala |
| author_sort | Gokul Chandrasekaran |
| collection | DOAJ |
| description | System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC’02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm’s exploration process by adjusting the equation for bat loudness (A0) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC’02 SoC benchmark circuits. |
| first_indexed | 2024-04-12T03:34:35Z |
| format | Article |
| id | doaj.art-73ca7673ca364541893bfc5572bf78f0 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T03:34:35Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-73ca7673ca364541893bfc5572bf78f02022-12-22T03:49:29ZengIEEEIEEE Access2169-35362022-01-011012619912621610.1109/ACCESS.2022.32249249964215Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT AlgorithmGokul Chandrasekaran0https://orcid.org/0000-0002-3569-9443Neelam Sanjeev Kumar1P. R. Karthikeyan2https://orcid.org/0000-0001-5340-5229K. Vanchinathan3Neeraj Priyadarshi4https://orcid.org/0000-0001-6620-6771Bhekisipho Twala5https://orcid.org/0000-0002-3452-9581Department of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Erode, IndiaDepartment of Biomedical Engineering, Saveetha School of Engineering, SIMATS, Chennai, IndiaDepartment of Electronics and Communication Engineering, Saveetha School of Engineering, SIMATS, Chennai, IndiaDepartment of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Erode, IndiaDepartment of Electrical Engineering, JIS College of Engineering, Kolkata, IndiaDigital Transformation Portfolio, Tshwane University of Technology, Pretoria, South AfricaSystem-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC’02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm’s exploration process by adjusting the equation for bat loudness (A0) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC’02 SoC benchmark circuits.https://ieeexplore.ieee.org/document/9964215/Test timesystem-on-chipmodified BAT algorithmBAT algorithmtest scheduling |
| spellingShingle | Gokul Chandrasekaran Neelam Sanjeev Kumar P. R. Karthikeyan K. Vanchinathan Neeraj Priyadarshi Bhekisipho Twala Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm IEEE Access Test time system-on-chip modified BAT algorithm BAT algorithm test scheduling |
| title | Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm |
| title_full | Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm |
| title_fullStr | Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm |
| title_full_unstemmed | Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm |
| title_short | Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm |
| title_sort | test scheduling and test time minimization of system on chip using modified bat algorithm |
| topic | Test time system-on-chip modified BAT algorithm BAT algorithm test scheduling |
| url | https://ieeexplore.ieee.org/document/9964215/ |
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