Low-Latency Hardware Masking with Application to AES
During the past two decades there has been a great deal of research published on masked hardware implementations of AES and other cryptographic primitives. Unfortunately, many hardware masking techniques can lead to increased latency compared to unprotected circuits for algorithms such as AES, due t...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Ruhr-Universität Bochum
2020-03-01
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| Series: | Transactions on Cryptographic Hardware and Embedded Systems |
| Subjects: | |
| Online Access: | https://tches.iacr.org/index.php/TCHES/article/view/8553 |