Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM
In this study, a common-mode voltage (CMV) reduction scheme based on carrier-based pulse-width modulation (PWM) is proposed for asymmetric dual three-phase hybrid active neutral-point-clamped (ADTP-HANPC) inverters. The fundamental concept is that the alignment sequence of multi-level gating signals...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10258156/ |
| _version_ | 1797668044330237952 |
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| author | Syed Mohammad Maaz Dong-Choon Lee |
| author_facet | Syed Mohammad Maaz Dong-Choon Lee |
| author_sort | Syed Mohammad Maaz |
| collection | DOAJ |
| description | In this study, a common-mode voltage (CMV) reduction scheme based on carrier-based pulse-width modulation (PWM) is proposed for asymmetric dual three-phase hybrid active neutral-point-clamped (ADTP-HANPC) inverters. The fundamental concept is that the alignment sequence of multi-level gating signals is adjusted to produce zero CMV or ones with equal magnitude and opposite polarities in the two individual loads. To achieve this objective, dynamic phase-shift PWM (DPSPWM) is implemented between the switches of the DTP-HANPC inverter. The DPSPWM outperforms existing CMV elimination methods in terms of efficiency, with a 20 % improvement. This is primarily owing to the lower number of switching transitions. Furthermore, the current and voltage THDs are reduced compared with the existing zero CMV space vector PWM (SVPWM). The effectiveness of the proposed method has been validated through simulations and experiments. These demonstrated a significant reduction (≥75.9%) in maximum CMV peaks. |
| first_indexed | 2024-03-11T20:23:21Z |
| format | Article |
| id | doaj.art-748bbf1785174c408dbb2e87fbf51424 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-11T20:23:21Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-748bbf1785174c408dbb2e87fbf514242023-10-02T23:00:48ZengIEEEIEEE Access2169-35362023-01-011110423410424310.1109/ACCESS.2023.331812410258156Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWMSyed Mohammad Maaz0https://orcid.org/0009-0009-7692-270XDong-Choon Lee1https://orcid.org/0000-0003-0618-7630Department of Electrical Engineering, Yeungnam University, Gyeongsan, South KoreaDepartment of Electrical Engineering, Yeungnam University, Gyeongsan, South KoreaIn this study, a common-mode voltage (CMV) reduction scheme based on carrier-based pulse-width modulation (PWM) is proposed for asymmetric dual three-phase hybrid active neutral-point-clamped (ADTP-HANPC) inverters. The fundamental concept is that the alignment sequence of multi-level gating signals is adjusted to produce zero CMV or ones with equal magnitude and opposite polarities in the two individual loads. To achieve this objective, dynamic phase-shift PWM (DPSPWM) is implemented between the switches of the DTP-HANPC inverter. The DPSPWM outperforms existing CMV elimination methods in terms of efficiency, with a 20 % improvement. This is primarily owing to the lower number of switching transitions. Furthermore, the current and voltage THDs are reduced compared with the existing zero CMV space vector PWM (SVPWM). The effectiveness of the proposed method has been validated through simulations and experiments. These demonstrated a significant reduction (≥75.9%) in maximum CMV peaks.https://ieeexplore.ieee.org/document/10258156/Common-mode voltage (CMV)dual three-phase (DTP)hybrid active neutral point clamped (HANPC)pulse-width modulation (PWM) |
| spellingShingle | Syed Mohammad Maaz Dong-Choon Lee Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM IEEE Access Common-mode voltage (CMV) dual three-phase (DTP) hybrid active neutral point clamped (HANPC) pulse-width modulation (PWM) |
| title | Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM |
| title_full | Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM |
| title_fullStr | Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM |
| title_full_unstemmed | Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM |
| title_short | Common-Mode Voltage Mitigation for Dual Three-Phase Three-Level ANPC Inverters Using Dynamic Phase-Shift PWM |
| title_sort | common mode voltage mitigation for dual three phase three level anpc inverters using dynamic phase shift pwm |
| topic | Common-mode voltage (CMV) dual three-phase (DTP) hybrid active neutral point clamped (HANPC) pulse-width modulation (PWM) |
| url | https://ieeexplore.ieee.org/document/10258156/ |
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