| Summary: | This paper presents the design of a buck converter for use in low-power system-on-chips (SoCs) with a ripple voltage small enough to directly power sensitive analog circuits without the help of low-dropout voltage regulators (LDOs). To minimize the ripple voltage while maximizing the converter’s light-load efficiency, we employ a pulse-frequency modulation (PFM) scheme and a fast duty-cycled comparator to control the converter’s output voltage. The duty cycling of the comparator, automatically performed by the Sleep State Controller (SSC), helps improve the light-load efficiency by 48%. Fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process with an active area of <inline-formula> <tex-math notation="LaTeX">$0.42 ~\mathrm {mm}^{2}$ </tex-math></inline-formula>, the proposed low-ripple buck converter achieves the ripple voltage of <inline-formula> <tex-math notation="LaTeX">$1.6~ \mathrm {mV_{pp}}$ </tex-math></inline-formula> and the overall efficiency of higher than 74.4% over the load current range from <inline-formula> <tex-math notation="LaTeX">$1.2 \mu \text{A}$ </tex-math></inline-formula> to 1.8 mA.
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