A low power and high speed decoder design based on FPGA
In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network...
| Main Authors: | , , |
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| Format: | Article |
| Language: | zho |
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National Computer System Engineering Research Institute of China
2018-04-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000080146 |
| _version_ | 1811198737435852800 |
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| author | Zhou Songjiang Li Shengchen Liu Ming |
| author_facet | Zhou Songjiang Li Shengchen Liu Ming |
| author_sort | Zhou Songjiang |
| collection | DOAJ |
| description | In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network as the codec algorithm with FPGA implementation. The system realizes the decoding of characters, and can be applied to the decoding of various multimedia information. Through ModelSim simulation and Xilinx ISE implementation, the hardware measurement are carried out, and the calculation accuracy, resource consumption, calculation speed and power consumption are analyzed. Experimental results show that the designed decoder can decode data correctly, the algorithm is efficient, scalable, the proposed system has the characteristics of low power consumption and high speed, and it can be widely used in a variety of low power, portable products. |
| first_indexed | 2024-04-12T01:36:17Z |
| format | Article |
| id | doaj.art-76a9e6308e824f45a41d2af3dd6b6472 |
| institution | Directory Open Access Journal |
| issn | 0258-7998 |
| language | zho |
| last_indexed | 2024-04-12T01:36:17Z |
| publishDate | 2018-04-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj.art-76a9e6308e824f45a41d2af3dd6b64722022-12-22T03:53:19ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982018-04-01444273210.16157/j.issn.0258-7998.1734863000080146A low power and high speed decoder design based on FPGAZhou Songjiang0Li Shengchen1Liu Ming2Institute of Information Photonics and Optical Communications，Beijing University of Posts and Telecommunications，Beijing 100876Institute of Information Photonics and Optical Communications，Beijing University of Posts and Telecommunications，Beijing 100876Institute of Information Photonics and Optical Communications，Beijing University of Posts and Telecommunications，Beijing 100876In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network as the codec algorithm with FPGA implementation. The system realizes the decoding of characters, and can be applied to the decoding of various multimedia information. Through ModelSim simulation and Xilinx ISE implementation, the hardware measurement are carried out, and the calculation accuracy, resource consumption, calculation speed and power consumption are analyzed. Experimental results show that the designed decoder can decode data correctly, the algorithm is efficient, scalable, the proposed system has the characteristics of low power consumption and high speed, and it can be widely used in a variety of low power, portable products.http://www.chinaaet.com/article/3000080146FPGAdecoderautoencoder neural networkhardware implementationhigh speed and low power consumption |
| spellingShingle | Zhou Songjiang Li Shengchen Liu Ming A low power and high speed decoder design based on FPGA Dianzi Jishu Yingyong FPGA decoder autoencoder neural network hardware implementation high speed and low power consumption |
| title | A low power and high speed decoder design based on FPGA |
| title_full | A low power and high speed decoder design based on FPGA |
| title_fullStr | A low power and high speed decoder design based on FPGA |
| title_full_unstemmed | A low power and high speed decoder design based on FPGA |
| title_short | A low power and high speed decoder design based on FPGA |
| title_sort | low power and high speed decoder design based on fpga |
| topic | FPGA decoder autoencoder neural network hardware implementation high speed and low power consumption |
| url | http://www.chinaaet.com/article/3000080146 |
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