Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures

Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designe...

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Main Authors: Francisco J. Villa, Manuel Acacio Sánchez, José Manuel García Carrasco
Format: Article
Language:English
Published: Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata 2006-04-01
Series:Journal of Computer Science and Technology
Subjects:
Online Access:https://journal.info.unlp.edu.ar/JCST/article/view/823
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author Francisco J. Villa
Manuel Acacio Sánchez
José Manuel García Carrasco
author_facet Francisco J. Villa
Manuel Acacio Sánchez
José Manuel García Carrasco
author_sort Francisco J. Villa
collection DOAJ
description Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics.
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spelling doaj.art-76e6fdccc82e4ae69085ff511422489e2022-12-21T20:26:11ZengPostgraduate Office, School of Computer Science, Universidad Nacional de La PlataJournal of Computer Science and Technology1666-60461666-60382006-04-0160117517Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors ArchitecturesFrancisco J. Villa0Manuel Acacio Sánchez1José Manuel García Carrasco2Dept. Ingeniería y Tecnología de Computadores, Universidad de Murcia, SpainDept. Ingeniería y Tecnología de Computadores, Universidad de Murcia, SpainDept. Ingeniería y Tecnología de Computadores, Universidad de Murcia, SpainChip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics.https://journal.info.unlp.edu.ar/JCST/article/view/823chip-multiprocessorsmemory hierarchy organizationcache miss latencycache storage useenergy-aware techniques
spellingShingle Francisco J. Villa
Manuel Acacio Sánchez
José Manuel García Carrasco
Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
Journal of Computer Science and Technology
chip-multiprocessors
memory hierarchy organization
cache miss latency
cache storage use
energy-aware techniques
title Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
title_full Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
title_fullStr Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
title_full_unstemmed Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
title_short Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
title_sort toward energy efficient high performance organizations of the memory hierarchy in chip multiprocessors architectures
topic chip-multiprocessors
memory hierarchy organization
cache miss latency
cache storage use
energy-aware techniques
url https://journal.info.unlp.edu.ar/JCST/article/view/823
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AT josemanuelgarciacarrasco towardenergyefficienthighperformanceorganizationsofthememoryhierarchyinchipmultiprocessorsarchitectures