FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a s...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-10-01
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| Series: | Applied Sciences |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2076-3417/11/21/10183 |
| _version_ | 1797512785035264000 |
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| author | Miroslaw Chmiel Robert Czerwinski Andrzej Malcher |
| author_facet | Miroslaw Chmiel Robert Czerwinski Andrzej Malcher |
| author_sort | Miroslaw Chmiel |
| collection | DOAJ |
| description | The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions. |
| first_indexed | 2024-03-10T06:06:35Z |
| format | Article |
| id | doaj.art-78b598c90b95431c88c62d8ff0c0a080 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-10T06:06:35Z |
| publishDate | 2021-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-78b598c90b95431c88c62d8ff0c0a0802023-11-22T20:29:01ZengMDPI AGApplied Sciences2076-34172021-10-0111211018310.3390/app112110183FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLCMiroslaw Chmiel0Robert Czerwinski1Andrzej Malcher2Department of Digital Systems, Silesian University of Technology, Adademicka Str. 16, 44-100 Gliwice, PolandDepartment of Digital Systems, Silesian University of Technology, Adademicka Str. 16, 44-100 Gliwice, PolandDepartment of Electronics, Electrical Engineering and Microelectronics, Silesian University of Technology, Adademicka Str. 16, 44-100 Gliwice, PolandThe article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.https://www.mdpi.com/2076-3417/11/21/10183programmable logic controllers (PLC)countersIEC 61131-3field programmable gate arrays (FPGA)function blockscentral processing units (CPU) |
| spellingShingle | Miroslaw Chmiel Robert Czerwinski Andrzej Malcher FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC Applied Sciences programmable logic controllers (PLC) counters IEC 61131-3 field programmable gate arrays (FPGA) function blocks central processing units (CPU) |
| title | FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC |
| title_full | FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC |
| title_fullStr | FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC |
| title_full_unstemmed | FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC |
| title_short | FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC |
| title_sort | fpga implementation of iec 61131 3 based hardware aided counters for plc |
| topic | programmable logic controllers (PLC) counters IEC 61131-3 field programmable gate arrays (FPGA) function blocks central processing units (CPU) |
| url | https://www.mdpi.com/2076-3417/11/21/10183 |
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