| Summary: | The growing complexity and size of integrated circuits has made functional verification a huge challenge. As the control center of integrated circuit hardware design, any design errors in the Instruction Pipeline Control Unit (IPCU) will put the entire chip at significant risk. Verification of the IPCU has accordingly become a substantial challenge for test engineers. Taking a 32-bit VLIW DSP as the research goal, this paper proposes a directional random verification method for IPCU based on the instruction reordering strategy (InstRO). First, according to the symmetry of input and output of the instruction pipeline, this method considers several functional components as a whole and establishes a high-level reference model based on the instruction reordering strategy (InstRO-Model), thereby both shielding the complex logic inside the hardware design and reducing the complexity of the verification model. Second, by automatically generating random test stimuli, the constraints of which can be adjusted in a particular direction, effective intensive testing of different functional points of the design under test (DUT) is realized, and code coverage and functional coverage are both improved. Finally, the test stimuli are input into the InstRO-Model and the DUT at the same time. As the input and output of the InstRO-Model also have symmetry with the input and output of the DUT, an automatic comparison of the verification results is realized via assertions. This approach greatly reduces the manpower and time required for verification and improves the verification efficiency. Experiments and practical application results show that this method can increase the code coverage to more than 99%. In particular, efficient directional random verification can be carried out for the weak points in the instruction pipeline control verification and the function points that are difficult to manually simulate and traverse, which greatly improves the verification efficiency and verification integrity of the IPCU.
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