Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit
Today, mobile multimedia systems that use the H.261 / 3/4/5, MPEG-1/2/4 and JPEG standards for encoding / decoding video, audio and images are widely spread [1–4]. The core of these standards is the discrete cosine transform (DCT) of I, II, III ... VIII types [DCT]. Wide support in a h...
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| Format: | Article |
| Language: | Russian |
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Educational institution «Belarusian State University of Informatics and Radioelectronics»
2021-06-01
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| Series: | Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki |
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| Online Access: | https://doklady.bsuir.by/jour/article/view/3070 |
| _version_ | 1797880949157920768 |
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| author | V. V. Kliuchenia |
| author_facet | V. V. Kliuchenia |
| author_sort | V. V. Kliuchenia |
| collection | DOAJ |
| description | Today, mobile multimedia systems that use the H.261 / 3/4/5, MPEG-1/2/4 and JPEG standards for encoding / decoding video, audio and images are widely spread [1–4]. The core of these standards is the discrete cosine transform (DCT) of I, II, III ... VIII types [DCT]. Wide support in a huge number of multimedia applications of the JPEG format by circuitry and software solutions and the need for image coding according to the L2L scheme determines the relevance of the problem of creating a decorrelated transformation based on DCT and methods for rapid prototyping of processors for computing an integer DCT on programmable systems on a FPGA chip. At the same time, such characteristics as structural regularity, modularity, high computational parallelism, low latency and power consumption are taken into account. Direct and inverse transformation should be carried out according to the “whole-to-whole” processing scheme with preservation of the perfective reconstruction of the original image (the coefficients are represented by integer or binary rational numbers; the number of multiplication operations is minimal, if possible, they are excluded from the algorithm). The wellknown integer DCTs (BinDCT, IntDCT) do not give a complete reversible bit to bit conversion. To encode an image according to the L2L scheme, the decorrelated transform must be reversible and implemented in integer arithmetic, i. e. the conversion would follow an “integer-to-integer” processing scheme with a minimum number of rounding operations affecting the compactness of energy in equivalent conversion subbands. This article shows how, on the basis of integer forward and inverse DCTs, to create a new universal architecture of decorrelated transform on FPGAs for transformational image coding systems that operate on the principle of “lossless-to-lossy” (L2L), and to obtain the best experimental results for objective and subjective performance compared to comparable compression systems. |
| first_indexed | 2024-04-10T03:12:23Z |
| format | Article |
| id | doaj.art-795591e2b3b84cdcb0863ae1c59a6e9a |
| institution | Directory Open Access Journal |
| issn | 1729-7648 |
| language | Russian |
| last_indexed | 2024-04-10T03:12:23Z |
| publishDate | 2021-06-01 |
| publisher | Educational institution «Belarusian State University of Informatics and Radioelectronics» |
| record_format | Article |
| series | Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki |
| spelling | doaj.art-795591e2b3b84cdcb0863ae1c59a6e9a2023-03-13T07:33:21ZrusEducational institution «Belarusian State University of Informatics and Radioelectronics»Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki1729-76482021-06-0119351310.35596/1729-7648-2021-19-3-5-131687Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuitV. V. Kliuchenia0Belarusian State University Informatics and RadioelectronicsToday, mobile multimedia systems that use the H.261 / 3/4/5, MPEG-1/2/4 and JPEG standards for encoding / decoding video, audio and images are widely spread [1–4]. The core of these standards is the discrete cosine transform (DCT) of I, II, III ... VIII types [DCT]. Wide support in a huge number of multimedia applications of the JPEG format by circuitry and software solutions and the need for image coding according to the L2L scheme determines the relevance of the problem of creating a decorrelated transformation based on DCT and methods for rapid prototyping of processors for computing an integer DCT on programmable systems on a FPGA chip. At the same time, such characteristics as structural regularity, modularity, high computational parallelism, low latency and power consumption are taken into account. Direct and inverse transformation should be carried out according to the “whole-to-whole” processing scheme with preservation of the perfective reconstruction of the original image (the coefficients are represented by integer or binary rational numbers; the number of multiplication operations is minimal, if possible, they are excluded from the algorithm). The wellknown integer DCTs (BinDCT, IntDCT) do not give a complete reversible bit to bit conversion. To encode an image according to the L2L scheme, the decorrelated transform must be reversible and implemented in integer arithmetic, i. e. the conversion would follow an “integer-to-integer” processing scheme with a minimum number of rounding operations affecting the compactness of energy in equivalent conversion subbands. This article shows how, on the basis of integer forward and inverse DCTs, to create a new universal architecture of decorrelated transform on FPGAs for transformational image coding systems that operate on the principle of “lossless-to-lossy” (L2L), and to obtain the best experimental results for objective and subjective performance compared to comparable compression systems.https://doklady.bsuir.by/jour/article/view/3070dctdiscrete cosine transforml2llossless-to-lossyarchitecturefpga (field-programmable gate array)block staircase structuralparameterizationblsp |
| spellingShingle | V. V. Kliuchenia Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki dct discrete cosine transform l2l lossless-to-lossy architecture fpga (field-programmable gate array) block staircase structuralparameterization blsp |
| title | Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit |
| title_full | Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit |
| title_fullStr | Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit |
| title_full_unstemmed | Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit |
| title_short | Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit |
| title_sort | design of a discrete сosine transformation processor for image compression systems on a losless to lossy circuit |
| topic | dct discrete cosine transform l2l lossless-to-lossy architecture fpga (field-programmable gate array) block staircase structuralparameterization blsp |
| url | https://doklady.bsuir.by/jour/article/view/3070 |
| work_keys_str_mv | AT vvkliuchenia designofadiscretesosinetransformationprocessorforimagecompressionsystemsonaloslesstolossycircuit |