A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era
Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current reali...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Transactions on Quantum Engineering |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9205650/ |
| _version_ | 1818588483026944000 |
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| author | Siyuan Niu Adrien Suau Gabriel Staffelbach Aida Todri-Sanial |
| author_facet | Siyuan Niu Adrien Suau Gabriel Staffelbach Aida Todri-Sanial |
| author_sort | Siyuan Niu |
| collection | DOAJ |
| description | Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity. |
| first_indexed | 2024-12-16T09:25:28Z |
| format | Article |
| id | doaj.art-7a0c59d35bee44f199eef25ef19c141d |
| institution | Directory Open Access Journal |
| issn | 2689-1808 |
| language | English |
| last_indexed | 2024-12-16T09:25:28Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Transactions on Quantum Engineering |
| spelling | doaj.art-7a0c59d35bee44f199eef25ef19c141d2022-12-21T22:36:40ZengIEEEIEEE Transactions on Quantum Engineering2689-18082020-01-01111410.1109/TQE.2020.30265449205650A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ EraSiyuan Niu0https://orcid.org/0000-0003-4683-381XAdrien Suau1https://orcid.org/0000-0002-2412-7298Gabriel Staffelbach2Aida Todri-Sanial3https://orcid.org/0000-0001-8573-2910LIRMM, University of Montpellier, Montpellier, FranceLIRMM, University of Montpellier, Montpellier, FranceCentre Européen de Recherche et de Formation Avancée en Calcul Scientifique, Toulouse, FranceLIRMM, University of Montpellier, Montpellier, FranceDue to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.https://ieeexplore.ieee.org/document/9205650/Noisy intermediate-scale quantum (NISQ) hardwarequantum computingqubit mapping |
| spellingShingle | Siyuan Niu Adrien Suau Gabriel Staffelbach Aida Todri-Sanial A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era IEEE Transactions on Quantum Engineering Noisy intermediate-scale quantum (NISQ) hardware quantum computing qubit mapping |
| title | A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era |
| title_full | A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era |
| title_fullStr | A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era |
| title_full_unstemmed | A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era |
| title_short | A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era |
| title_sort | hardware aware heuristic for the qubit mapping problem in the nisq era |
| topic | Noisy intermediate-scale quantum (NISQ) hardware quantum computing qubit mapping |
| url | https://ieeexplore.ieee.org/document/9205650/ |
| work_keys_str_mv | AT siyuanniu ahardwareawareheuristicforthequbitmappingprobleminthenisqera AT adriensuau ahardwareawareheuristicforthequbitmappingprobleminthenisqera AT gabrielstaffelbach ahardwareawareheuristicforthequbitmappingprobleminthenisqera AT aidatodrisanial ahardwareawareheuristicforthequbitmappingprobleminthenisqera AT siyuanniu hardwareawareheuristicforthequbitmappingprobleminthenisqera AT adriensuau hardwareawareheuristicforthequbitmappingprobleminthenisqera AT gabrielstaffelbach hardwareawareheuristicforthequbitmappingprobleminthenisqera AT aidatodrisanial hardwareawareheuristicforthequbitmappingprobleminthenisqera |