Noise Power Minimization in CMOS Brain-Chip Interfaces
This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-01-01
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| Series: | Bioengineering |
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| Online Access: | https://www.mdpi.com/2306-5354/9/2/42 |
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| author | Lorenzo Stevenazzi Andrea Baschirotto Giorgio Zanotto Elia Arturo Vallicelli Marcello De Matteis |
| author_facet | Lorenzo Stevenazzi Andrea Baschirotto Giorgio Zanotto Elia Arturo Vallicelli Marcello De Matteis |
| author_sort | Lorenzo Stevenazzi |
| collection | DOAJ |
| description | This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV<sub>RMS</sub> of noise power and 50 µV<sub>RMS</sub> of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µV<sub>RMS</sub>) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain. |
| first_indexed | 2024-03-09T22:35:49Z |
| format | Article |
| id | doaj.art-7a2b614a8ee548d0a24a6c67235cdec9 |
| institution | Directory Open Access Journal |
| issn | 2306-5354 |
| language | English |
| last_indexed | 2024-03-09T22:35:49Z |
| publishDate | 2022-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Bioengineering |
| spelling | doaj.art-7a2b614a8ee548d0a24a6c67235cdec92023-11-23T18:48:11ZengMDPI AGBioengineering2306-53542022-01-01924210.3390/bioengineering9020042Noise Power Minimization in CMOS Brain-Chip InterfacesLorenzo Stevenazzi0Andrea Baschirotto1Giorgio Zanotto2Elia Arturo Vallicelli3Marcello De Matteis4Department of Physics, University of Milano-Bicocca, Piazza della Scienza 3, 20126 Milano, ItalyDepartment of Physics, University of Milano-Bicocca, Piazza della Scienza 3, 20126 Milano, ItalyDepartment of Physics, University of Milano-Bicocca, Piazza della Scienza 3, 20126 Milano, ItalySection of Milano Bicocca, National Institute of Nuclear Physics, Piazza della Scienza 3, 20126 Milano, ItalyDepartment of Physics, University of Milano-Bicocca, Piazza della Scienza 3, 20126 Milano, ItalyThis paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV<sub>RMS</sub> of noise power and 50 µV<sub>RMS</sub> of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µV<sub>RMS</sub>) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain.https://www.mdpi.com/2306-5354/9/2/42biological neural networksbiosensorsneural engineeringanalog integrated circuitslow-noise amplifier |
| spellingShingle | Lorenzo Stevenazzi Andrea Baschirotto Giorgio Zanotto Elia Arturo Vallicelli Marcello De Matteis Noise Power Minimization in CMOS Brain-Chip Interfaces Bioengineering biological neural networks biosensors neural engineering analog integrated circuits low-noise amplifier |
| title | Noise Power Minimization in CMOS Brain-Chip Interfaces |
| title_full | Noise Power Minimization in CMOS Brain-Chip Interfaces |
| title_fullStr | Noise Power Minimization in CMOS Brain-Chip Interfaces |
| title_full_unstemmed | Noise Power Minimization in CMOS Brain-Chip Interfaces |
| title_short | Noise Power Minimization in CMOS Brain-Chip Interfaces |
| title_sort | noise power minimization in cmos brain chip interfaces |
| topic | biological neural networks biosensors neural engineering analog integrated circuits low-noise amplifier |
| url | https://www.mdpi.com/2306-5354/9/2/42 |
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