41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology
A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DF...
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MDPI AG
2023-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/18/3912 |
| _version_ | 1797580460936658944 |
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| author | Yongzheng Zhan Tuo Li Xiaofeng Zou Qingsheng Hu Lianming Li Lu Zhang |
| author_facet | Yongzheng Zhan Tuo Li Xiaofeng Zou Qingsheng Hu Lianming Li Lu Zhang |
| author_sort | Yongzheng Zhan |
| collection | DOAJ |
| description | A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm<sup>2</sup>, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz. |
| first_indexed | 2024-03-10T22:50:20Z |
| format | Article |
| id | doaj.art-7aa2b0af5a5c4c36b1c8ad686e18c0f9 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T22:50:20Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-7aa2b0af5a5c4c36b1c8ad686e18c0f92023-11-19T10:23:07ZengMDPI AGElectronics2079-92922023-09-011218391210.3390/electronics1218391241.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS TechnologyYongzheng Zhan0Tuo Li1Xiaofeng Zou2Qingsheng Hu3Lianming Li4Lu Zhang5Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Co., Ltd., Jinan 250101, ChinaShandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Co., Ltd., Jinan 250101, ChinaShandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Co., Ltd., Jinan 250101, ChinaInstitute of RF- & OE-ICs, Southeast University, Nanjing 210096, ChinaPurple Mountain Laboratories, Nanjing 211111, ChinaShandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Co., Ltd., Jinan 250101, ChinaA high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm<sup>2</sup>, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz.https://www.mdpi.com/2079-9292/12/18/3912high speedpre-interleaverDFE error propagationparallel PRBS generatorregister |
| spellingShingle | Yongzheng Zhan Tuo Li Xiaofeng Zou Qingsheng Hu Lianming Li Lu Zhang 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology Electronics high speed pre-interleaver DFE error propagation parallel PRBS generator register |
| title | 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology |
| title_full | 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology |
| title_fullStr | 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology |
| title_full_unstemmed | 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology |
| title_short | 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology |
| title_sort | 41 6 gb s high depth pre interleaver for dfe error propagation in 65 nm cmos technology |
| topic | high speed pre-interleaver DFE error propagation parallel PRBS generator register |
| url | https://www.mdpi.com/2079-9292/12/18/3912 |
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