41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DF...

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Bibliographic Details
Main Authors: Yongzheng Zhan, Tuo Li, Xiaofeng Zou, Qingsheng Hu, Lianming Li, Lu Zhang
Format: Article
Language:English
Published: MDPI AG 2023-09-01
Series:Electronics
Subjects:
high speed
pre-interleaver
DFE error propagation
parallel PRBS generator
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Online Access:https://www.mdpi.com/2079-9292/12/18/3912

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