Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells
Micro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules to handle heavy computational loads, they have substantially reached a limit in size, power ef...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-09-01
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| Series: | Signals |
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| Online Access: | https://www.mdpi.com/2624-6120/3/3/38 |
| _version_ | 1797482413066027008 |
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| author | Raj Mouli Jujjavarapu Alwin Poulose |
| author_facet | Raj Mouli Jujjavarapu Alwin Poulose |
| author_sort | Raj Mouli Jujjavarapu |
| collection | DOAJ |
| description | Micro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules to handle heavy computational loads, they have substantially reached a limit in size, power efficiency, and similar avenues. Due to these constraints, many manufacturers and corporate entities are trying many ways to optimize these mini beasts. One such approach is to design microprocessors based on the specified operating system. This approach came to the limelight when many companies launched their microprocessors. In this paper, we will look into one method of using an arithmetic logic unit (ALU) module for internet of things (IoT)-enabled devices. A specific set of operations is added to the classical ALU to help fast computational processes in IoT-specific programs. We integrated a compression module and a fast multiplier based on the Vedic algorithm in the 16-bit ALU module. The designed ALU module is also synthesized under a 32-nm HVT cell library from the Synopsys database to generate an overview of the areal efficiency, logic levels, and layout of the designed module; it also gives us a netlist from this database. The synthesis provides a complete overview of how the module will be manufactured if sent to a foundry. |
| first_indexed | 2024-03-09T22:32:00Z |
| format | Article |
| id | doaj.art-7bcf459c63af4faa90387dbdce2f322b |
| institution | Directory Open Access Journal |
| issn | 2624-6120 |
| language | English |
| last_indexed | 2024-03-09T22:32:00Z |
| publishDate | 2022-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Signals |
| spelling | doaj.art-7bcf459c63af4faa90387dbdce2f322b2023-11-23T18:55:20ZengMDPI AGSignals2624-61202022-09-013362064110.3390/signals3030038Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT CellsRaj Mouli Jujjavarapu0Alwin Poulose1School of Electronics Engineering, Kyungpook National University, 80 Daehak-ro, Buk-gu, Daegu 41566, KoreaCenter for ICT & Automotive Convergence, Kyungpook National University, 80 Daehak-ro, Buk-gu, Daegu 41566, KoreaMicro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules to handle heavy computational loads, they have substantially reached a limit in size, power efficiency, and similar avenues. Due to these constraints, many manufacturers and corporate entities are trying many ways to optimize these mini beasts. One such approach is to design microprocessors based on the specified operating system. This approach came to the limelight when many companies launched their microprocessors. In this paper, we will look into one method of using an arithmetic logic unit (ALU) module for internet of things (IoT)-enabled devices. A specific set of operations is added to the classical ALU to help fast computational processes in IoT-specific programs. We integrated a compression module and a fast multiplier based on the Vedic algorithm in the 16-bit ALU module. The designed ALU module is also synthesized under a 32-nm HVT cell library from the Synopsys database to generate an overview of the areal efficiency, logic levels, and layout of the designed module; it also gives us a netlist from this database. The synthesis provides a complete overview of how the module will be manufactured if sent to a foundry.https://www.mdpi.com/2624-6120/3/3/38microprocessorsoperating systemsinternet of things (IoT)arithmetic logic unit (ALU)compression moduleVedic multiplier |
| spellingShingle | Raj Mouli Jujjavarapu Alwin Poulose Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells Signals microprocessors operating systems internet of things (IoT) arithmetic logic unit (ALU) compression module Vedic multiplier |
| title | Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells |
| title_full | Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells |
| title_fullStr | Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells |
| title_full_unstemmed | Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells |
| title_short | Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells |
| title_sort | verilog design synthesis and netlisting of iot based arithmetic logic and compression unit for 32 nm hvt cells |
| topic | microprocessors operating systems internet of things (IoT) arithmetic logic unit (ALU) compression module Vedic multiplier |
| url | https://www.mdpi.com/2624-6120/3/3/38 |
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