Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths
Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC’s D01GH (100 nm gate l...
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| Format: | Article |
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MDPI AG
2021-01-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/2/134 |
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| author | Sergio Colangeli Walter Ciccognani Patrick Ettore Longhi Lorenzo Pace Julien Poulain Rémy Leblanc Ernesto Limiti |
| author_facet | Sergio Colangeli Walter Ciccognani Patrick Ettore Longhi Lorenzo Pace Julien Poulain Rémy Leblanc Ernesto Limiti |
| author_sort | Sergio Colangeli |
| collection | DOAJ |
| description | Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC’s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader’s convenience. |
| first_indexed | 2024-03-09T05:24:24Z |
| format | Article |
| id | doaj.art-7bf7176d099647bcbd15409312f4d97f |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T05:24:24Z |
| publishDate | 2021-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-7bf7176d099647bcbd15409312f4d97f2023-12-03T12:38:14ZengMDPI AGElectronics2079-92922021-01-0110213410.3390/electronics10020134Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate LengthsSergio Colangeli0Walter Ciccognani1Patrick Ettore Longhi2Lorenzo Pace3Julien Poulain4Rémy Leblanc5Ernesto Limiti6Electronics Engineering, University of Roma Tor Vergata, Via del Politecnico 1, 00133 Roma, ItalyElectronics Engineering, University of Roma Tor Vergata, Via del Politecnico 1, 00133 Roma, ItalyElectronics Engineering, University of Roma Tor Vergata, Via del Politecnico 1, 00133 Roma, ItalyElectronics Engineering, University of Roma Tor Vergata, Via del Politecnico 1, 00133 Roma, ItalyOMMIC SAS, 2 rue du Moulin, 94453 Limeil Brévannes, FranceOMMIC SAS, 2 rue du Moulin, 94453 Limeil Brévannes, FranceElectronics Engineering, University of Roma Tor Vergata, Via del Politecnico 1, 00133 Roma, ItalyMotivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC’s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader’s convenience.https://www.mdpi.com/2079-9292/10/2/134gallium nitride on siliconHEMTcharacterizationmodelingscalable SSECnoise temperatures |
| spellingShingle | Sergio Colangeli Walter Ciccognani Patrick Ettore Longhi Lorenzo Pace Julien Poulain Rémy Leblanc Ernesto Limiti Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths Electronics gallium nitride on silicon HEMT characterization modeling scalable SSEC noise temperatures |
| title | Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths |
| title_full | Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths |
| title_fullStr | Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths |
| title_full_unstemmed | Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths |
| title_short | Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths |
| title_sort | linear characterization and modeling of gan on si hemt technologies with 100 nm and 60 nm gate lengths |
| topic | gallium nitride on silicon HEMT characterization modeling scalable SSEC noise temperatures |
| url | https://www.mdpi.com/2079-9292/10/2/134 |
| work_keys_str_mv | AT sergiocolangeli linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT walterciccognani linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT patrickettorelonghi linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT lorenzopace linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT julienpoulain linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT remyleblanc linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths AT ernestolimiti linearcharacterizationandmodelingofganonsihemttechnologieswith100nmand60nmgatelengths |