Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology
The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manu...
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MDPI AG
2023-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/3/778 |
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| author | Gabriele Ciarpi Danilo Monda Marco Mestice Daniele Rossi Sergio Saponara |
| author_facet | Gabriele Ciarpi Danilo Monda Marco Mestice Daniele Rossi Sergio Saponara |
| author_sort | Gabriele Ciarpi |
| collection | DOAJ |
| description | The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device. |
| first_indexed | 2024-03-11T09:47:00Z |
| format | Article |
| id | doaj.art-7c3ccbc2e96c4cbeadadea6b34eed2e9 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T09:47:00Z |
| publishDate | 2023-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-7c3ccbc2e96c4cbeadadea6b34eed2e92023-11-16T16:31:23ZengMDPI AGElectronics2079-92922023-02-0112377810.3390/electronics12030778Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS TechnologyGabriele Ciarpi0Danilo Monda1Marco Mestice2Daniele Rossi3Sergio Saponara4Dipartimento di Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, ItalyDipartimento di Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, ItalyDipartimento di Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, ItalyDipartimento di Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, ItalyDipartimento di Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, ItalyThe current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device.https://www.mdpi.com/2079-9292/12/3/778CMOSvoltage-controlled oscillatorring oscillatorcurrent mode logichigh temperatureintegrated circuit |
| spellingShingle | Gabriele Ciarpi Danilo Monda Marco Mestice Daniele Rossi Sergio Saponara Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology Electronics CMOS voltage-controlled oscillator ring oscillator current mode logic high temperature integrated circuit |
| title | Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology |
| title_full | Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology |
| title_fullStr | Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology |
| title_full_unstemmed | Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology |
| title_short | Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology |
| title_sort | asymmetric 5 5 ghz three stage voltage controlled ring oscillator in 65 nm cmos technology |
| topic | CMOS voltage-controlled oscillator ring oscillator current mode logic high temperature integrated circuit |
| url | https://www.mdpi.com/2079-9292/12/3/778 |
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