Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation
Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter o...
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| Format: | Article |
| Language: | English |
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MDPI AG
2024-01-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/14/1/3 |
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| author | Prashanth Barla Hemalatha Shivarama Ganesan Deepa Ujjwal Ujjwal |
| author_facet | Prashanth Barla Hemalatha Shivarama Ganesan Deepa Ujjwal Ujjwal |
| author_sort | Prashanth Barla |
| collection | DOAJ |
| description | Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. |
| first_indexed | 2024-04-24T18:08:09Z |
| format | Article |
| id | doaj.art-7c6dca5de11d4e56bba4b1da72580aa1 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-24T18:08:09Z |
| publishDate | 2024-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-7c6dca5de11d4e56bba4b1da72580aa12024-03-27T13:48:57ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682024-01-01141310.3390/jlpea14010003Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-ComputationPrashanth Barla0Hemalatha Shivarama1Ganesan Deepa2Ujjwal Ujjwal3Department of Computer Science and Engineering, Manipal Institute of Technology, Manipal Academey of Higher Education, Manipal 576104, Karnataka, IndiaDepartment of Computer Science and Engineering, Manipal Institute of Technology, Manipal Academey of Higher Education, Manipal 576104, Karnataka, IndiaDepartment of Computer Science and Engineering, Manipal Institute of Technology, Manipal Academey of Higher Education, Manipal 576104, Karnataka, IndiaDepartment of Computer Science and Engineering, Manipal Institute of Technology, Manipal Academey of Higher Education, Manipal 576104, Karnataka, IndiaHybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.https://www.mdpi.com/2079-9268/14/1/3magnetic tunnel junctionspin-hall effectspin transfer torquenon-volatilevoltage-gated spin orbit torquein-memory-computation |
| spellingShingle | Prashanth Barla Hemalatha Shivarama Ganesan Deepa Ujjwal Ujjwal Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation Journal of Low Power Electronics and Applications magnetic tunnel junction spin-hall effect spin transfer torque non-volatile voltage-gated spin orbit torque in-memory-computation |
| title | Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation |
| title_full | Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation |
| title_fullStr | Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation |
| title_full_unstemmed | Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation |
| title_short | Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation |
| title_sort | design and assessment of hybrid mtj cmos circuits for in memory computation |
| topic | magnetic tunnel junction spin-hall effect spin transfer torque non-volatile voltage-gated spin orbit torque in-memory-computation |
| url | https://www.mdpi.com/2079-9268/14/1/3 |
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