A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) cod...

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Bibliographic Details
Main Authors: Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
LDPC
decoder
NAND
SSD
Online Access:https://ieeexplore.ieee.org/document/9874844/

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